Process for making wafers for ion implantation monitoring

Semiconductor device manufacturing: process – With measuring or testing

Reexamination Certificate

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C438S015000

Reexamination Certificate

active

06485992

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a process for making silicon wafers and, more particularly, to such a process which produces silicon wafers with low and uniform surface stress for use as control wafers to be used in ion implantation.
Un-patterned, bare silicon wafers are used by device manufacturers to monitor and control their ion implantation tools. The monitoring procedure involves the following steps: 1) measuring the pre-implantation stress in the witness or control wafer using laser modulated thermal reflectivity; 2) implanting the wafer with ion dosage; 3) measuring the post-implant stress; and 4) using the delta (post-pre) measurement to determine the implant dosage. This method works very well for high dosage implants. However, for low dosage implants, the high variability, both wafer-to-wafer and within-wafer, of the pre-implant stress signal, increases the uncertainty of the measurement significantly. It had been thought that the wafer-to-wafer and within-wafer variability of the stress was caused by residual lattice damage caused by slicing, grinding, lapping and polishing or just uncertainty of the measurement.
In most cases, this has been determined not to be so. Rather, the chemical films that are formed on wafers during post-polish cleaning or post-Epi processing are the primary source of stress in the front surface silicon lattice. Control of these films allows one to control the lattice stress to low and uniform values that are preferred for control or witness wafers used in ion implantation.
The Themaprobe TP420 (made by Therma-Wave of Fremont, Calif.) is one instrument commonly used in the industry to measure laser modulated thermal reflectivity of ion implanted wafers. The “TW30” and “TW0” signals are both measures of residual stress in silicon. For example, TW
30
of a wafer before ion implantation may read 100 TW
30
units; then, after a 100 keV/W11 ions/cm{circumflex over ( )}2 implantation may read 300 TW
30
units. In this example, the post-implant signal is only 3 times greater than the pre-implant signal. This problem becomes worse for lower dose and lower energy implants (Kirby et al., Nuclear Instruments and Methods in Physics Research B21, 550, 1987). It is therefore highly desirable to have an implant witness wafer that has an initial TW signal that is <30 TW and that is very uniform.
Silicon wafer makers are currently selling wafers with one of three types of surface finishes: SCl oxides, ozone oxides or post Epi air oxides. All three of these oxides have problems with respect to TW. The SCl oxides and ozone oxides have TW
30
signals that are 100 and 300, respectively. And, an Epi wafer that doesn't have an intentionally grown chemical oxide has regions of low TW
30
(<30) and high TW
30
(>>30).
There is a need, therefore, for a process for making a silicon wafer having a TW
0
reading less than approximately 30 across the entire wafer.
SUMMARY OF THE INVENTION
Among the several objects of the invention may be noted the provision of a novel process for making a silicon wafer with low and uniform surface stress; the provision of such a process in which a wafer is hydrogen terminated or hydrogen terminated and oxidized with an oxidant having a standard reduction potential less than approximately 1.77 volts; the provision of such a process in which the feed wafer is a wafer with a freshly grown epitaxial layer or a wafer freshly stripped of oxide; and the provision of such a process which produces a wafer with at least 8 angstroms of silicon oxide thereon. Other objects and features will be in part apparent and in part pointed out hereinafter.
Briefly, the present invention is directed to a process for making a silicon wafer with low and uniform surface stress by growing at least approximately 8 angstroms of silicon oxide thereon to produce a wafer for use as a control wafer in ion implantation, which method comprises the steps of:
(a) subjecting a feed wafer substantially free of oxide or having less than approximately 4 angstroms of silicon oxide thereon to hydrogen termination of the silicon surface; or
(b) subjecting such a feed wafer to said hydrogen termination followed by subjecting the resulting wafer to treatment with an oxidant having a standard reduction potential less than approximately 1.77 volts; the wafer resulting from either step (a) or (b) having a TWO reading less than approximately 30 across the entire wafer.


REFERENCES:
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patent: 5849627 (1998-12-01), Linn et al.
patent: 5907188 (1999-05-01), Nakajima et al.
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patent: 6133150 (2000-10-01), Nakajima et al.
patent: 6249026 (2001-06-01), Matsumoto et al.
patent: 6326318 (2001-12-01), Watanabe et al.

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