Process for making self-aligned conductive via structures

Details Process for making self-aligned conductive via structures Process for making self-aligned conductive via structures

1997-06-30

2000-10-17

Everhart, C.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257748, 257765, 257771, 438688, 438669, 438671, H01L 2348

Patent

active

061336351

ABSTRACT:
Disclosed is a process for making a self-aligning conductive via structure in a semiconductor device. The process includes forming a first interconnect metallization layer over an oxide layer. Forming an etch stop layer over the first interconnect metallization layer. Forming a conductive via metallization layer over the etch stop layer. Forming a hard mask layer over the conductive via metallization layer. The process further includes producing a conductive via and an interconnect line, where the conductive via is formed from a portion of the conductive via metallization layer, and the interconnect line is formed from a portion of the first interconnect metallization layer. The conductive via is substantially aligned with the underlying interconnect line.

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