Metal working – Barrier layer or semiconductor device making – Barrier layer device making
Patent
1996-05-20
1998-02-10
Niebling, John
Metal working
Barrier layer or semiconductor device making
Barrier layer device making
H01G 915
Patent
active
057164207
ABSTRACT:
A process is provided for making a package-type fused solid electrolytic capacitor. In the process, a capacitor element having a chip body and an anode wire is first mounted between an opposed pair of anode and cathode leads with the anode wire attached to the anode lead, the cathode lead having a tip cutout. Then, a material fuse wire is connected to the chip body and the cathode lead with an intermediate portion of the material fuse wire located in the tip cutout of the cathode lead. Then, a resin package is molded to enclose the capacitor element together with the material fuse wire. Then, the resin package is separated from the anode and cathode leads by cutting. Then, an anode terminal electrode and a cathode terminal electrode are formed on the resin package in electrical conduction with the anode wire and the fuse wire, respectively.
REFERENCES:
patent: 5057973 (1991-10-01), Gouvernelle et al.
patent: 5099397 (1992-03-01), Edson et al.
patent: 5179507 (1993-01-01), Iijima
patent: 5216584 (1993-06-01), Okazaki et al.
patent: 5315474 (1994-05-01), Kuriyama
Bilodeau Thomas G.
Niebling John
Rohm & Co., Ltd.
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