Process for making MOS devices for low-temperature operation

Details Process for making MOS devices for low-temperature operation Process for making MOS devices for low-temperature operation

1990-06-26

1992-02-25

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 57, 437101, 437937, H01L 21336, H01L 21203

Patent

active

050913255

ABSTRACT:
Electric charge is supplied to a circuit node being in a charge storing state within a signal processor in response to a signal-processing commencing signal. The processor is operated in a low-temperature range, for example, in the range of temperature below 200K. By this structure, a leakage current is reduced, a high degree of integration equivalent to that of a dynamic circuit can be obtained, and the simplicity of a static circuit not requiring any complicated internal/external timing signals can be realized. Also disclosed is a semiconductor device, and method of forming such semiconductor device, for operation in a range of temperatures below 100.degree. K. The device has, in a silicon surface region where the channel of the device is formed, a low impurity concentration layer (between the source and drain regions of the device). Such low impurity concentration layer is formed by evaporating amorphous silicon on a surface region of a semiconductor region of the device and passing the device through a low-temperature annealing process, the low impurity concentration layer having a lower total impurity concentration than that of the semiconductor region thereunder and having a thickness not more than 100 nm.

REFERENCES:
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patent: 4315781 (1982-02-01), Henderson
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patent: 4498224 (1985-02-01), Maeguchi
patent: 4514747 (1985-04-01), Miyata et al.
patent: 4679303 (1987-07-01), Chen
patent: 4700212 (1987-10-01), Okazawa
Chang, "Built-in Channel FET" IBM Technical Disclosure Bulletin, vol. 14, No. 4, Sep. 1971.

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