Process for making indium gallium arsenide devices

Details Process for making indium gallium arsenide devices Process for making indium gallium arsenide devices

1988-08-22

1989-05-09

Edlow, Martin H.

357 16, 357 55, H01L 2980

Patent

active

048293474

ABSTRACT:
Junction field effect transistors are described with unusually short gates and a self-aligned structure which permits close approach of the source and drain electrodes to the p-n junction. Such devices have high speed, high gain and are usefully combined with other field effect transistors in integrated circuits.

REFERENCES:
patent: 4048712 (1977-09-01), Buiatti
patent: 4075652 (1978-02-01), Umebachi
patent: 4236166 (1980-11-01), Cho et al.
patent: 4424525 (1984-01-01), Mimura
patent: 4549197 (1985-10-01), Brehan
Umbachi et al, Elect. Devices, Aug. 1975, pp. 613-614.
"In.sub.0.53 Ga.sub.0.47 As Submicrometer FET's Grown by MBE", IEEE Electron Device Letters, vol. EDL-4, No. 7, Jul. 1983, pp. 252-254.
Part B: "Materials and Operating Characteristics", Heterostructure Lasers, Academic Press, New York, 1978, by H. C. Casey, Jr. and M. B. Panish.
"A Self-Aligned In.sub.0.53 Ga.sub.0.47 As Junction Field Effect Transistor Grown by Molecular Beam Epitaxy", IEEE Electron Device Letters, vol. EDL-5, No. 7, Jul. 1984, pp. 285-287.

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