Process for making high density mask ROM

Details Process for making high density mask ROM Process for making high density mask ROM

1999-06-18

2001-04-24

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

C438S275000, C438S297000

Reexamination Certificate

active

06221698

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a method for making a semiconductor memory device and, more particularly, to a method of making a high density mask-type read only memory.
BACKGROUND OF THE INVENTION
Read only memory (ROM) devices are semiconductor integrated circuits widely used in microprocessor-based systems to permanently store information even when power is off. ROM devices are particularly well suited for applications where a large volume of devices having identical data are required or for storing data that is repeatedly used. An example of such an application is the BIOS on personal computers. ROM devices store binary signals as an array of active elements that are typically programmed as part of the fabrication process by the integrated circuit manufacturer according to a customer's specifications.
Conventional mask ROM devices include NOR-type and NAND-type. A NOR-type ROM is formed by connecting in parallel the sources and the drains of the memory transistors. Alternatively, connecting the sources and the drains of the memory transistors in series forms a NAND-type ROM.
As shown in
FIGS. 1-3
fabrication of a conventional flat-cell mask ROM begins with a semiconductor silicon substrate (
10
) doped with P-type impurities. Buried bit lines (
11
) that will constitute source/drain regions are formed by implanting N-type impurities into multiple parallel strip shaped regions of the substrate. A gate oxide layer (
12
), typically silicon oxide formed by thermal oxidation, is then formed over the substrate (
10
). Gate electrodes (
13
) are then formed orthogonal to the buried bit lines (
11
), constituting word lines for the memory array of the mask ROM device. Convention coding procedure requires that a photoresist layer (
14
) be applied covering the surface of the substrate (
10
) while leaving the coding openings (
15
) exposed. Impurity ions are then implanted into the exposed channel regions of the selected memory cells.
The channel regions for the memory cell transistors lies in the region of the substrate between every two adjacent bit lines beneath the word lines. The memory cell transistors are coded as either blocking or conducting. A 1 or 0 data bit can be defined as either state. If a cell is implanted with P-type impurities, the cell is set to have a high threshold voltage effectively setting the memory cell to a permanently OFF state representing, for example, the storage of binary digit of 0. Cells without implanted impurities have a low threshold voltage setting the memory cell to a permanently ON state representing, for example, the storage of a binary 1.
As a result of semiconductor device manufacturers striving to improve performance and reduce cost, the size of ROM devices continues to shrink while the density of ROM devices continues to increase. A problem arises because the reduced space between adjacent bit lines makes leakage current arising from the P-type implants and word line parasitic capacitance relatively more detrimental.
U.S. Pat. No. 5,504,036 to Chung et al. discloses one solution to these problems. By using a liquid-phase deposition process to form a thick code oxide, Chung et al. produce permanently OFF cells on the semiconductor substrate. A liquid-phase deposition process, however, cannot easily be integrated into CMOS manufacturing.
U.S. Pat. No. 5,480,823 to Hsu discloses the use of a thick oxide to produce normally OFF cells. Hsu teaches the growth of a thick oxide layer on areas of a substrate that have been defined by photolithography and subsequent etch of a silicon nitride layer. Growth of the thick oxide in this manner, however, produces a “birds beak” on the buried bit line edge.
In light of the foregoing, there is a need for a process to manufacture ROM with a thick code oxide that can be easily integrated into standard CMOS manufacturing.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to method for manufacturing a mask programmable ROM including the steps of forming an oxide layer with a thickness greater than about 1000Å on a semiconductor substrate, forming a first mask layer over the oxide layer and patterning the first mask layer to form bit lines, removing regions of the oxide layer within the bit lines to expose the semiconductor substrate, ion implanting conductivity imparting dopants into the exposed substrate to form buried bit line regions, removing the first mask layer and forming a second mask layer, printing a code pattern and forming coding openings that expose portions of the substrate between the bit lines, removing the second mask layer, growing a gate oxide within the coding openings, depositing a conducting layer on remaining regions of the oxide layer, the buried bit line regions, and the gate oxide, and forming a plurality of conducting gate structures constituting word lines for the mask ROM.
In another aspect of the present invention, there is provided a method for manufacturing a mask programmable ROM integrated into a CMOS fabrication process including the steps of growing an oxide layer with a thickness greater than about 1000Å on a P-type semiconductor substrate, depositing a first mask layer on the oxide layer and forming a bit line pattern, removing regions of the first mask layer to form bit lines, removing regions of the oxide layer within the bit line area to expose the semiconductor substrate, ion implanting conductivity imparting dopants into the exposed substrate to form buried bit line regions, removing the first mask layer, forming a second mask layer and patterning the second mask layer to form coding openings exposing areas of the semiconductor substrate, removing the second mask layer, forming a gate oxide within the coding openings, depositing a polysilicon layer, forming a plurality of polysilicon gate electrodes oriented orthogonally to the bit lines constituting word lines for said mask ROM.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description serve to explain the principles of the invention.


REFERENCES:
patent: 4750024 (1988-06-01), Schreck
patent: 5480823 (1996-01-01), Hsu
patent: 5504030 (1996-04-01), Chung et al.
patent: 5585296 (1996-12-01), Chung et al.

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