Process for making and programming a flash memory array

Details Process for making and programming a flash memory array Process for making and programming a flash memory array

1996-05-14

1997-10-28

Graybill, David

Fishing, trapping, and vermin destroying

437 52, H01L 21265, H01L 218247

Patent

active

056817703

ABSTRACT:
A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.

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