Process for making a semiconductor MOS transistor

Fishing – trapping – and vermin destroying

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437 44, 437200, H01L 218234

Patent

active

056041381

ABSTRACT:
A process for forming an MOS semiconductor device having an LDD structure is disclosed, which may include the steps of: forming a first insulating layer on a semiconductor substrate; forming a conductive layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a third insulating layer on the second insulating layer; forming an etch inhibiting layer pattern for forming an over-sized gate on a relevant area of the second insulating layer; removing the second and third insulating layers and the conductive layer excluding the portions protected from the etch inhibiting layer, so as to form a stacked pattern consisting of the residual second insulating layer/the third insulating layer/the conductive layer; forming a first impurity ion buried layer on a relevant portion of the semiconductor substrate utilizing the stacked pattern for formation of a source/drain region; removing the etch inhibiting layer; removing an edge portion of the remaining second insulating layer of the stacked pattern for forming the final gate; removing the residual third insulating layer of the stacked pattern; etching the residual conductive layer by using the partly removed second insulating layer as the mask to form the final gate; forming a second impurity ion buried layer on the relevant portion of the semiconductor substrate for forming the LDD structure; forming a fourth insulating layer on the whole surface of the wafer; and activating the first and second ion buried layers.

REFERENCES:
patent: 5208476 (1993-05-01), Inoue
Wolf et al., "Silicon Processing for the VLSI Era vol. I: Process Technology", Lattice Press, 1986, pp. 384-385.
Ghandhi, "VLSI Fabrication Principles Silicon and Gallium Arsenide", John Wiley & Sons, 1983, pp. 327-328, 522-524.

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