Fishing – trapping – and vermin destroying
Patent
1989-03-30
1990-10-02
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437203, 437 68, 437150, 437238, 437241, 437160, 148DIG43, 148DIG126, 148DIG103, 148DIG147, H01L 21335
Patent
active
049607235
ABSTRACT:
An improved method for making a self-aligned vertical field effect transistor is provided wherein a nitride sidewall spacer is formed around a polysilicon gate, and an oxide sidewall spacer, which may be heavily doped with an n-type dopant, is formed covering the silicon nitride sidewall spacer. The silicon nitride sidewall spacer allows the oxide sidewall spacer of a conventional self-aligned vertical field effect transistor process to be removed partially or completely before making ohmic contact to the source thus increasing the contact area between the source and the source electrode and eliminating reliability problems related to n-type doped oxide in contact with aluminum electrodes.
REFERENCES:
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patent: 4593302 (1986-06-01), Lidow et al.
patent: 4644637 (1987-02-01), Temple
patent: 4735680 (1988-04-01), Yen
patent: 4753897 (1988-06-01), Lund et al.
Mori et al., "An Insulated Gate . . . ", IEEE IEDM Technical Digest, 1988, pp. 813-816.
Barbee Joe E.
Hearn Brian E.
Langley Stuart T.
Motorola Inc.
Quach Tin
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