Process for making a high density split gate nonvolatile memory

Details Process for making a high density split gate nonvolatile memory Process for making a high density split gate nonvolatile memory

1988-01-25

1989-08-29

Hearn, Brian E.

Fishing, trapping, and vermin destroying

148DIG82, 148DIG102, 437 27, 437150, 437924, 437984, 357 235, 357 91, 357 239, H01L 2710, H01L 2978

Patent

active

048617300

ABSTRACT:
A process is disclosed for producing a high density split gate nonvolatile memory cell which includes a floating gate and a control gate that is formed above the floating gate. The drain region is self-aligned to the floating gate and the source region is self-aligned to the control gate. Fully self-aligned implantation is made possible by the process and structure using self-aligned etch. Programming of the memory cell uses standard EPROM programming, and erasing is accomplished by Fowler-Nordheim tunneling or photoemission. The memory cell can be made with a reduced cell size and read current uniformity is obtained.

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Gheorghe Samachisa et al., "A 128 Flash EEPROM Using Double-Polysilicon Technology", from IEEE Journal of Solid State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 676-683.
Abstract of above-identified Samachisa et al. article from 1987 IEEE Solid-State Circuits Conference Digest of Technical Papers, Feb. 25, 1987, pp. 76 and 77.

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