Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
2005-12-20
2005-12-20
Smoot, Stephen W. (Department: 2813)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
C438S016000
Reexamination Certificate
active
06977183
ABSTRACT:
A process which addresses the problem of transient defects comprises first processing one or more test chips on a substrate to reveal one or more potential transient defects during subsequent processing of all of the chips on the substrate; identifying the exact locations of such potential transient defects on one or more chips of a silicon substrate; forming a file containing the coordinates of each potential transient defect on the chip; converting the file into a CAD image layer capable of displaying such potential transient defects; and displaying such potential transient defects superimposed over a CAD image of the actual circuit to permit visual inspection of the compound CAD image and to permit optional action to be taken in view of such potential transient defects. In another embodiment of the invention, the file containing the locations of the potential transient defects is transmitted to a metrology apparatus such as a critical dimension (CD) scanning electron microscope (SEM) which monitors the potential transient defect addresses during processing of the chip. The two embodiments of the invention may be practiced in the alternative or in combination with one another.
REFERENCES:
patent: 5943551 (1999-08-01), Schemmel et al.
patent: 2002/0114506 (2002-08-01), Hiroi et al.
patent: 200368815 (2001-08-01), None
Almog et al., “Size matters:defect detectability in reticle and wafer inspection including advanced aerial image simulation for defect printability”, Journal, vol. 3546, pp. 139-144, 1998.
Ito,“Automated system for the LSI fine pattern inspection based on comparison of SIM images and CAD data”, IEEE, pp. 544-549, 1995.
N. Kuji et al., “FINDER: A CAD System-Based Electron Beam Tester for Fault Diagnosis of VLSI Circuits,” IEEE Transactions on Computer-Aided Design, vol. CAD-5, No. 2, Apr. 1986, pp. 313-319.
“High-Resolution Imaging System 2351”, KLA-Tencor Product Brochure, ©2002, pp. 1-2.
“Klarity Defect: Automated Analysis and Defect Data Management System”, KLA-Tencor Procduct Brochure, ©2000, pp. 1-4.
KLA-Tencor Technologies Corporation
Taylor John P.
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