Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Subsequent separation into plural bodies
Reexamination Certificate
2000-02-02
2002-02-12
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Subsequent separation into plural bodies
C438S520000
Reexamination Certificate
active
06346459
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to processes for fabricating integrated circuits and, more particularly, to a method for integrating semiconductor devices prefabricated on different substrates using implant-induced cut, alignment, bonding onto a host substrate, and interconnecting the devices monolithically integrated.
BACKGROUND OF THE INVENTION
Monolithic integration of different types of semiconductor devices on certain substrates is difficult to realize because of the poisoning of a first type device by a processing step required to fabricate a second type device. The prior art describes several approaches to overcome this problem. In particular it is suggested to fabricate two types of devices respectively on separate substrates, and then to cut the first type of device from its substrate. The first type device is then positioned on a host substrate that contains prefabricated devices of the second type.
Conventional processes for lift off and transfer of semiconductor devices onto alien substrate includes the following sequence of steps:
Fabrication of the semiconductor device on a first substrate.
Protecting the devices that are to survive a succeeding cutting step by deposition of a protective coating.
Cutting a device-containing layer from the first substrate.
Placing the layer on a second substrate.
Fixing the device layer on the second substrate.
Removing the protective coating to release the semiconductor devices.
The prior art is represented by the following references: (1) U.S. Pat. No. 4,846,931 to Gmitter et al., “Method for Lifting-Off Epitaxial Films”; (2) “Transfer of Structured and Patterned Thin Films Using the Smart-Cut™ Process”, Aspar et al., Electronic Letters, v.32, No.21, pp.1985-1986, 1996; (3) WO98/33209, Bruel et al., “Method for Obtaining a Thin Film, in Particular Semiconductor, Comprising a Protected Ion Zone and Involving an Ion Implantation” (1998); (4) “Substrate Bonding Techniques for CMOS Processed Wafers”, van der Groen et al., J. Micromech.Microeng., v.7, pp.108-110, 1997; and (5) “Transfer of Patterned Ion-Cut Silicon Layers”, C. H. Yun et al., Applied Physics Letters, V.73, No.19, pp.2772-2774, 1998.
The above cited prior art uses either a sacrificial layer etch (1) or an ion-cut (1,3,4,5) to delaminate the device containing layer. The older etch technique is limited to small area (~1 cm
2
) device transferals. The newer ion-cut technique (1) allows batch processing and achieves wafer size device layer transferals. The ion-cut technique uses implantation of hydrogen (preferably in the form of protons) into the device containing wafer and the formation of a continuous embedded gaseous layer from the implanted hydrogen ions, thus releasing the top device layer from the rest of the wafer.
All known ion-cut techniques (1,3,4,5) avoid hydrogen implantation through sensitive device areas in the semiconductor device layer to be transferred. A protective layer is temporarily deposited on top of the sensitive device areas of each semiconductor device before the hydrogen implantation (3). Some processes protect only the most sensitive parts of the devices to be transferred. There are several disadvantages that result from the ion-cut-based process for device transfers to a new substrate. Among the disadvantages are lowered yields and device densities.
Accordingly, it is an object of the invention to provide an improved method for lift-off and transfer of semiconductor devices to new substrates.
It is another object of the invention to provide a method for lift-off and transfer of semiconductor devices to new substrates that requires less steps than prior art processes.
It is a further object of the invention to provide an improved method for lift-off and transfer of semiconductor devices to new substrates that does not require the deposition of protective layers during the lift-off process.
SUMMARY OF THE INVENTION
The process of the present invention does not employ protective layers during the lift-off process. All semiconductor devices are subjected to a proton implantation, causing the devices to become inoperable immediately after the implantation. This is due to an accumulation of defects in the devices during the implantation. The semiconductor devices incorporate metallic, dielectric, semiconductive, and interface portions. While the metallic portions are not affected by the implantation, the remaining portions are. The dielectric portions accumulate positive or negative charges, the interfaces experience a rise in surface states and the semiconductor portions accumulate radiation-induced defects. Importantly, the invention makes use of the fact that all changes caused by the proton implantation are thermally unstable and are reversible. Accordingly, application of an additional thermal treatment to the semiconductor structure, in a temperature range (i.e., 425° C.-800° C.) that exceeds the thermal stability limit of the most stable defect introduced during implantation, enabling a reversal of the defects.
REFERENCES:
patent: 4391651 (1983-07-01), Yoder
patent: 4846931 (1989-07-01), Gmitter et al.
patent: 5374564 (1994-12-01), Bruel
patent: 5863830 (1999-01-01), Bruel et al.
patent: 5882987 (1999-03-01), Srikrishnan
patent: 5953622 (1999-09-01), Lee et al.
patent: 6211041 (2001-04-01), Oruga
patent: WO98/33209 (1998-07-01), None
Applied Physics Letters, vol. 73, No. 19, Nov. 9, 1998, pp. 2772-2774, C. H. Yun et al., “Transfer of Patterned Ion-cut Silicon Layers”.
Electronics Letters, vol. 32, No. 21, Oct. 10, 1996, pp. 1985-1986, B. Aspar et al., “Transfer of Structured and Patterned Thin Silicon Films Using the Smart-Cut® Process”.
J. Micromech. Microeng., vol. 7 (1997) pp. 108-110, S. van der Groen, et al., “Substrate Bonding Techniques for CMOS Processed Wafers”.
Carr William N.
Usenko Alexander Y
Dang Phuc T.
Nelms David
Silicon Wafer Technologies Inc.
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