Process for integration of gate dielectric layers having differe

Details Process for integration of gate dielectric layers having differe Process for integration of gate dielectric layers having differe

1994-10-24

1995-07-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437 57, 437979, H01L 218238

Patent

active

054321140

ABSTRACT:
A process for fabricating an IGFET integrated circuit having two gate dielectric layers with different parameters is provided. Typically, the process is used for fabrication of dual voltage CMOS integrated circuits. The integrated circuit may include high voltage transistors having a first gate dielectric thickness and low voltage transistors having a second gate dielectric thickness. A first gate dielectric layer and a first gate layer for the high voltage transistors are formed over active regions of a substrate. The device is patterned to expose low voltage transistor areas, and the first gate dielectric layer and the first gate layer are removed in the low voltage transistor areas. Then, a second gate dielectric layer and a second gate layer for the low voltage transistors are formed on the device. The device is patterned to expose the high voltage transistor areas, and the second gate dielectric layer and the second gate layer are removed in the high voltage transistor areas. The gate dielectric layers are protected against contamination during processing and do not come in contact with photoresist.

REFERENCES:
patent: 4635347 (1987-01-01), Lien et al.
patent: 4859619 (1989-08-01), Wu et al.
patent: 4866002 (1989-09-01), Shizukuishi et al.
patent: 5057449 (1991-10-01), Lowrey et al.
patent: 5254489 (1993-10-01), Nakata

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