Process for integrating alignment mark and trench device

Details Process for integrating alignment mark and trench device Process for integrating alignment mark and trench device

2003-07-28

2004-07-27

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C438S975000, C438S427000, C438S243000, C438S386000, C257S797000

Reexamination Certificate

active

06767800

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a semiconductor process. More particularly, it relates to a simplified process for integrating an alignment mark and a trench device to reduce fabrication cost.
2. Description of the Related Art
Lithography is one of most important processes for fabricating semiconductor integrated circuits. Lithography is used in the transfer of a pattern onto a thin film or the fabrication of a mask for ion implantation. In general, lithography is conducted many times in the production of is semiconductor circuits. In a lithography step, however, one critical factor is pattern alignment. When a wafer is processed to form patterns in the different thin films deposited thereon, the wafer must be properly aligned relative to the previous pattern. Conventionally, an alignment mark (AM) is used for alignment before carrying out photo-exposure.
In general, alignment marks are formed outside the device region, such as the scribe line of a wafer, at the same time as a thin film such as an insulating layer or a conductive layer is patterned.
FIGS. 1
a
to
1
d
are cross-sections showing a conventional process for integrating an alignment mark and a trench device. First, in
FIG. 1
a
, a substrate
100
, such as a silicon wafer, is provided. The substrate
100
has a device region
10
and an alignment mark region
20
which is at the scribe line of the wafer
100
.
Next, a patterned masking layer
105
is formed on the substrate
100
. The patterned masking layer
105
can be composed of a pad oxide layer
102
and a thicker overlying silicon nitride layer
104
. Next, the substrate
100
is etched using the patterned masking layer
105
as an etch mask to form deep trenches
110
a
and
110
b
therein. The deep trench
110
a
is on the device region
10
and the trench
110
b
having a width larger than the deep trench
110
a
is on the alignment mark region
20
.
Next, trench capacitors
118
a
and
118
b
are respectively formed in the lower portion of the deep trenches
110
a
and
110
b
. The trench capacitor
118
a
includes a top plate
116
a
, a capacitor dielectric layer
114
a
, and a bottom plate
112
a
. Also, the trench capacitor
118
b
includes a top plate
116
b
, a capacitor dielectric layer
114
b
, and a bottom plate
112
b
. Next, collar insulating layers
117
a
and
117
b
are respectively formed on the trench capacitors
118
a
and
118
b
and over the sidewall of the deep trenches
110
a
and
110
b
. Thereafter, conductive layers
120
a
and
120
b
, such as polysilicon, are respectively formed in the deep trenches
110
a
and
110
b
, which have a height substantially equal to the collar insulating layers
117
a
and
117
b.
Next, a conductive layer
122
, such as polysilicon, is formed on the masking layer
105
and fills in the deep trenches
110
a
and
110
b.
Next, in
FIG. 1
b
, chemical mechanical polishing (CMP) is performed on the conductive layer
122
to respectively leave a portion of the conductive layers
122
a
and
122
b
in the deep trenches
110
a
and
110
b.
Next, in
FIG. 1
c
, the conductive layers
122
a
and
122
b
are etched to leave a portion of the conductive layers
124
a
and
124
b
in the deep trenches
110
a
and
110
b
, respectively. The conductive layer
120
a
and the remaining conductive layer
124
a
in the deep trench
110
a
are used as a wiring layer for the trench capacitor
118
a
. In addition, the trench capacitor
118
b
, the conductive layer
120
b
, and the remaining conductive layer
124
b
are used as an alignment mark.
Since the trench capacitor
118
b
and the conductive layers
120
b
and
124
b
are formed in the deep trench
110
b
, the step height of the substrate
100
on the alignment mark region
20
is reduced, lowering the image contrast of the alignment mark.
Accordingly, in
FIG. 1
d
, a patterned photoresist layer (not shown) is formed on the masking layer
105
by lithography to completely cover the deep trench
110
a
and expose the deep trench
110
b
only. Thereafter, the conductive layer
124
b
is completely removed and then the underlying conductive layer
120
b
and the collar insulating layer
117
b
are partially removed by etching using the patterned photoreist layer as a mask to leave a portion of the conductive layer
120
c
and the collar insulating layer
117
c
, thereby increasing the step height of the substrate
100
on the alignment mark region
20
. However, such a process is complex, thus increasing fabrication cost and the time required thereby.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a novel process for integrating an alignment mark and a trench device, thereby simplifying the process to reduce fabrication cost and time and increase throughput.
According to the object of the invention, a process for integrating an alignment mark and a trench device are provided. First, a substrate having first and second trenches is provided, wherein the second trench used as the alignment mark is wider than the first trench. Next, the trench device is formed in each of the low portions of the first and second trenches, and then a first conductive layer is formed on the trench device in each of the first and second trenches. Thereafter, a second conductive layer is formed overlying the substrate filling in the first trench and is simultaneously and conformably formed over the inner surface of the second trench. Finally, the second conductive layer and a portion of the first conductive layer in the second trench are removed and simultaneously leave a portion of the second conductive layer in the first trench by an etch back process, wherein the etch back process employs chemical mechanic polishing to remove the second conductive layer overlying the substrate.
Moreover, the first and second conductive layers can be a polysilicon layer, which have a thickness of about 2000Å to 4000Å.


REFERENCES:
patent: 5889335 (1999-03-01), Kuroi et al.
patent: 5893744 (1999-04-01), Wang
patent: 6043133 (2000-03-01), Jang et al.
patent: 6049137 (2000-04-01), Jang et al.
patent: 6100158 (2000-08-01), Lee et al.
patent: 6218262 (2001-04-01), Kuroi et al.
patent: 6218266 (2001-04-01), Sato et al.
patent: 6303460 (2001-10-01), Iwamatsu
patent: 6440816 (2002-08-01), Farrow et al.
patent: 2002/0192926 (2002-12-01), Schroeder et al.
patent: 2002134701 (2002-05-01), None

Affiliated with

Also associated with

Rating

Process for integrating alignment mark and trench device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for integrating alignment mark and trench device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for integrating alignment mark and trench device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3192573