Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including isolation structure
Reexamination Certificate
1999-07-27
2001-07-17
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including isolation structure
C438S360000
Reexamination Certificate
active
06261914
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for producing a semiconductor device, and more particularly to a method for improving uniformity of a chemical mechanical polishing (CMP) operation used in producing the semiconductor device.
2. Description of the Related Art
Conventional systems utilize shallow trench isolation (STI) in advanced integrated circuits to electrically isolate neighboring devices. Chemical mechanical polishing (CMP) is often used to pattern insulators in semiconductor trenches or conductors in insulating trenches. In many applications, the polishing is stopped only after all the material has been removed from the field regions.
However, oftentimes this operation results in over-polishing of the material in wide trenches.
For example,
FIGS. 1A-1D
illustrate a conventional process which is relatively simple, and is extendable to sub-quarter micron dimensions. In FIG.
1
A, a pad oxide
11
is grown by thermal oxidation of a silicon substrate
10
. Thereafter, a pad nitride, formed for example of SiN
12
, is deposited on the SiO
2
layer. Then, the trenches are etched.
In
FIG. 1B
, a SiO
2
layer
14
is deposited to fill the trenches.
In step
1
C, the SiO
2
layer
14
is patterned by CMP.
Finally in step
1
D, the pad nitride and pad oxide are stripped, and a sacrificial oxide
15
is grown.
However, a problem with the conventional process is that the polishing process used to pattern the SiO
2
isolation, as shown in
FIG. 1C
, may result in localized variations in the SiO
2
thickness. This is a problem, and could result in the resulting device “failing” during operation.
That is, in regions where the trenches are wide or the density of the active area is low, such as in region C of
FIG. 1D
, there is excessive thinning of the SiO
2
. The excessive oxide thinning allows the gate to wrap around the active areas, resulting in a low threshold voltage for the affected devices. Again, this may cause the device(s) to fail.
Moreover, in regions where the active areas are wide or where there is a low density of trenches, there may be insufficient removal of the SiO
2
such as in region A in FIG.
1
D. The residual SiO
2
masks the pad nitride strip, and the pad nitride blocks subsequent implants and gate oxide growth, resulting in failing devices.
Localized variations in polishing resulting from variations in the pattern factor are also observed for other CMP processes. For example, such processes include metal CMP to produce damascene interconnects (e.g., see
FIGS. 3A-3C
described below) or studs, dielectric planarization over a gate stack (e.g., see
FIGS. 5A-5C
described below) or a metal stack, and polysilicon patterning in deep trenches.
In the case of metal CMP, there is generally an excessive removal of metal in regions with wide metal features (e.g., region C in FIG.
3
C), whereas there may be insufficient removal of metal in wide oxide regions (e.g., see region A in FIG.
3
C). The excessive thinning of metal results in high resistance, and increased circuit delays. The residual metal on top of the oxide can result in leakage between interconnects.
Thus, the conventional processes result in poor local uniformity of CMP of SiO
2
isolations and other structures. As a result, the devices produced may suffer failures.
SUMMARY OF THE INVENTION
In view of the foregoing problems of the conventional methods, an object of the present invention is to provide a method for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer.
In a first aspect of the present invention, a method of making a semiconductor device, includes forming an oxide layer on a silicon substrate, forming a nitride layer over the oxide layer, depositing one of a doped oxide layer and an undoped porous oxide layer on the nitride layer, etching trenches through the one of the doped layer and the undoped porous oxide layer, the nitride layer, and the oxide layer, depositing an undoped oxide layer to fill the trenches, and patterning the undoped oxide by chemical mechanical polishing (CMP).
With the unique and unobvious process of the present invention, uniformity of the CMP results using a self-aligned polishing rate enhancement layer.
REFERENCES:
patent: 4962064 (1990-10-01), Haskell et al.
patent: 5192706 (1993-03-01), Rodder
patent: 5362669 (1994-11-01), Boyd et al.
patent: 5459096 (1995-10-01), Venkatesan et al.
patent: 5494857 (1996-02-01), Cooperman et al.
patent: 5516625 (1996-05-01), McNamara et al.
patent: 5665202 (1997-09-01), Subramanian et al.
patent: 5691215 (1997-11-01), Dai et al.
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5733801 (1998-03-01), Gojohbori
patent: 5786262 (1998-07-01), Jang et al.
patent: 6017803 (2000-01-01), Wong
patent: 6150212 (2000-11-01), Divakaruni et al.
Divakaruni Ramachandra
Gambino Jeffrey Peter
Radens Carl J.
Stephens Jeremy K.
Booth Richard
Gurley Lynne A.
International Business Machines - Corporation
McGinn & Gibb PLLC
LandOfFree
Process for improving local uniformity of chemical... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for improving local uniformity of chemical..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for improving local uniformity of chemical... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2533976