Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-01-17
2003-04-01
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S952000
Reexamination Certificate
active
06541387
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention is directed to the fabrication of semiconductor devices and, more particularly, to the formation of a patterned hardmask layer atop a substrate.
In a known process, a patterned hardmask layer is formed by first depositing a layer of hardmask material atop a substrate. Then, one or more photoresist layers or other resist layers are deposited atop the hardmask layer, and portions of the resist layer are exposed using known methods such as optical, ion beam or electron beam lithography. The resist is then developed to remove either the exposed portions of the resist, when positive resist is used, or the unexposed portions of the resist, when negative resist is used. The remaining portions of the resist serve as a masking layer for a subsequent etching step of the hardmask layer, such as by wet etching, reactive ion etching or other plasma etching processes, so that the pattern of the resist is transferred to the hardmask layer. The hardmask layer may thereafter serve as a masking layer for etching the substrate or for etching other layers disposed between the hardmask and the substrate.
As newer generations of denser and/or faster devices are introduced, smaller feature sizes are required. The lithography tools needed to resolve the smaller feature sizes also typically have smaller depths of focus. As a result, thinner resist layers must be deposited atop the hardmask layer so that the entire thickness of the resist is exposed in all locations of the wafer and avoid unopened regions in the developed resist. The thinner resist layers provide a thinner mask layer for the subsequent etching of the hardmask so that the hardmask layer must be etched under conditions that have greater hardmask-to-resist etching selectivity and which are often more difficult to control. Further, the higher selectivity etching of the hardmask layer is typically carried out at lower plasma energies that are more prone to undercut of the hardmask layer.
Alternatively, a thinner hardmask layer may be deposited atop the substrate to permit less selective etching of the hardmask layer but which provides less masking for subsequent etching steps. The subsequent etching steps must be carried out with higher etching selectivities that are more difficult to control. Further, the deposition of thinner hardmask layer is also often difficult to control.
It is therefore desirable to provide a process of patterning the hardmask layer in a manner that avoids the above problems.
SUMMARY OF THE INVENTION
The present invention provides a process for patterning the hardmask layer. The hardmask layer is deposited after the resist layer is deposited and patterned so that the portions of the hardmask layer that are deposited atop the remaining resist are removed when the resist is removed.
In accordance with the invention, a semiconductor device is fabricated. A resist layer is deposited atop a substrate, and the resist layer is patterned to expose portions of the substrate. A hardmask layer is deposited atop the patterned resist layer and atop the exposed portion of the substrate. The patterned resist layer is removed so that only a portion of the hardmask layer that is atop the substrate remains.
In accordance with another aspect of the invention, a hardmask layer is formed atop a substrate in the manner described above.
The foregoing aspects, features and advantages of the present invention will be further appreciated when considered with reference to the following description of the preferred embodiments and accompanying drawings.
REFERENCES:
patent: 5837405 (1998-11-01), Tomofuji et al.
Isaac Stanetta
Lerner David Littenberg Krumholz & Mentlik LLP
Niebling John F.
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