Process for hardening active electronic components against ioniz

Details Process for hardening active electronic components against ioniz Process for hardening active electronic components against ioniz

1990-07-27

1995-03-14

Breneman, R. Bruce

Fishing, trapping, and vermin destroying

437 84, 437 89, 437 90, 117931, 117934, H01L 2120

Patent

active

053977351

DESCRIPTION:

BRIEF SUMMARY
The invention relates to a process for hardening active electronic components against ionizing radiations, and to hardened components produced on substrates of large dimensions, especially components which are of the CMOS type or bipolar.
In schematic terms, the radiation-material interaction breaks down into two types of effect: (i) the displacements of atoms due to phenomena of collisions with the charged or uncharged particles (protons, alpha particles, electrons, neutrons, etc . . . ) and (ii) the ionization phenomena due to the absorption of the electromagnetic radiation (.gamma. and X rays). These two effects are liable to cause transitory or cumulative damage to electronic components.
Thus, under the action of the electric field prevailing in a junction or in a biased insulator, the two populations of carriers created by the irradiation (photogenerated carriers) are separated; this prevents their immediate recombination.
With regard to semiconductor materials and circuits, this effect of separation of photogenerated electron-hole pairs is reflected in the appearance of photocurrents which induce parasitic phenomena. Thus, the "Single Event Upset" (SEU), that is to say the occasional and localized accidental changing of a logic level; thus, again, "the Upset", that is to say the accidental but non-localized changing of a logic level associated with the propagation in the circuit of the disturbances initiated by the radiations; thus, finally, the phenomenon of "latch-up", that is to say the initiation of a pn pn parasitic tracking which is self-maintained in the CMOS devices on a solid silicon substrate.
As regards the insulators (especially of silica), the ionization effects are essentially reflected by a trapping of the photogenerated holes. In fact, the mobility of the holes in SiO.sub.2 being lower by some five orders of magnitude than that of the electrons, in the course of a transitory irradiation, the latter are swept by the electric field, while the former, by reason of their low mobility, remain trapped. The result of this is, for the components of the MOS type, an accumulation of fixed charges in the gate oxide which induces a drift of the threshold voltage as well as breakdown phenomena when this gate oxide is very thin.
On the other hand, the accumulation of fixed charges in the field oxides may also induce a phenomenon of surface conduction (inversion or accumulation from the subjacent semiconductor), the effect of which is to short-circuit adjacent components.
Various solutions have been found to remedy the aforementioned disadvantages. These solutions (hardening solutions) are based, on the one hand, on modifications regarding the design of the circuits and, on the other hand, on modifications regarding the technology of construction of these circuits.
Thus, by adding a pair of crossed resistors in the scheme of the basic cell of a RAM memory, an increase is achieved in the RC time constant of this cell in such a manner that the transient effects associated with the "Single Event Upset" have disappeared before the cell has had time to flip over (see, for example, Andrews et al. IEEE Transactions on Nuclear Science, Vol. NS-29, December 1982).
With regard to the technology, a reduction is made in the volume of all the zones in which electric fields prevail (the thickness of the gate oxides, the dimensions of the well p in the CMOS components, etc...), guard rings are installed in order to avoid the formation of the parasitic path giving rise to the effect of latch-up, etc... (See, for example Ansell and Tirado, in VLSI Systems Design, September 1986, p. 28).
However, the most highly appreciated technologies for the elimination of the isolation Junctions and of the effect of "latch-up" are based on the use of thin layers of silicon on insulating or SOI ("Silicon On Insulator") substrates. Thus, the de facto elimination of the parasitic path passing through the semiconductor substrate is achieved, and, furthermore, as the insulation between components is made by engraving, the suppression

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