Process for grounding flat devices and integrated circuits

Details Process for grounding flat devices and integrated circuits Process for grounding flat devices and integrated circuits

1985-06-07

1987-10-20

Hearn, Brian E.

Fishing, trapping, and vermin destroying

148DIG56, 148DIG126, 148DIG135, 156631, 156649, 156662, 357 232, 357 41, 427 98, H01L 2178

Patent

active

047004673

ABSTRACT:
Grounding of source contacts (S) of flat devices and integrated circuits (of the FET type) is carried out according to the following process steps: a GaAs wafer is applied on a support and is covered on its free or rear face with photoresist; the latter is then etched along the border lines of the single FETs; the GaAs layer between contiguous FETs is removed also to make accessible the contacts S; a layer of noble metal is then deposited on the FET rear faces, so that it bridges the contacts S; the single metallized devices are disconnected from the initial support and finally are soldered to a package base.

REFERENCES:
patent: 3771219 (1973-11-01), Tuzi et al.
patent: 4317125 (1982-02-01), Hughes et al.
Ghandi, VLSI Fabrication Principles Silicon and Gallium Arsenide, John Wiley and Sons, New York, 1983, pp. 443-446, 453-455, 482-487 and 556-560.

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