Process for forming vertical bipolar transistors and high voltag

Details Process for forming vertical bipolar transistors and high voltag Process for forming vertical bipolar transistors and high voltag

1989-03-17

1990-04-17

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 31, 437 59, 437 34, 357 43, H01L 21265

Patent

active

049180266

ABSTRACT:
A process is used to form in a common substrate a PMOS transistor of the lightly doped drain (LDD) type, an NMOS transistor of the LDD type and a vertical n-p-n bipolar transistor. In particular: the steps used to form an n-type well for the PMOS transistor, and an n-type drain extension well for the NMOS transistor, are also used to form the n-type collector of the bipolar transistor; the steps used to form the p-type extension well for the PMOS transistor are also used to form the p-type base of the bipolar transistor, the source/drain implantation step for the NMOS transistor is also used to form the emitter and a contact region for the collector of the bipolar transistor; and the source/drain implantation step for the PMOS transistor is used to form a contact region for the base of the bipolar transistor.

REFERENCES:
patent: 3576475 (1971-04-01), Kranlage
patent: 4047217 (1977-09-01), McCaffrey
patent: 4475279 (1984-10-01), Gahle
patent: 4503603 (1985-03-01), Blossfeld
patent: 4717686 (1988-01-01), Jacobs
patent: 4752589 (1988-06-01), Schaber

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