Process for forming solid conductive vias in substrates

Details Process for forming solid conductive vias in substrates Process for forming solid conductive vias in substrates

1994-01-14

1995-10-03

Niebling, John

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Coating selected area

205162, 205186, 205222, 205224, 427 97, H05K 342, C25D 502

Patent

active

054549280

ABSTRACT:
A method of forming solid metal vias extending between the top and bottom surfaces of a substrate with the ends of the vias being substantially coplanar with the top and bottom surfaces. The method includes the steps of forming holes through the substrate, plating the interior of the holes with excess metal to fill the holes and extend beyond the ends of the holes, heating the substrate to cause the metal to melt and consolidate to form solid vias with domed ends, and lapping the top and bottom surfaces of the substrate to remove the domes. Conductive layers may then be formed over the vias. These layers may have windows over a portion of each via to provide an escape route for expanding fluids during further processing of the substrate.

REFERENCES:
patent: 3385773 (1968-05-01), Frantzen
patent: 4131516 (1978-12-01), Bakos et al.
patent: 4368106 (1983-01-01), Anthony
patent: 4808273 (1989-02-01), Hua et al.
patent: 5055425 (1991-10-01), Leibovitz et al.
patent: 5162260 (1992-11-01), Leibovitz et al.
Frederick A. Lowenheim, Electroplating, McGraw-Hill Book Co., New York, 1978, p. 59.

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