Process for forming silicon LC pixel cell having planar...

Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only

Reexamination Certificate

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C349S122000, C349S113000, C349S138000

Reexamination Certificate

active

06373543

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pixel cell array for silicon LC light valves, and in particular, to a pixel cell array having a planar alignment layer of uniform thickness formed over the active pixel electrodes.
2. Description of the Related Art
Liquid crystal displays (LCDs) are becoming increasingly prevalent in high-density projection display devices. These display devices typically include a light source which passes light through a light valve.
One of the methods for producing colors in a liquid crystal display is to sequentially project light having a wavelength corresponding to a primary color onto a single light valve. Color sequential light valves create a spectrum of color within the range of the human perception by switching between a set of discrete primary colors. Typically, red, green, and blue are the primary tri-stimulus colors used to create the remaining colors of the spectrum.
Specifically, during projection of each primary color, the light intensity is modulated such that combination of the intensities of the primary colors in sequence produces the desired color. The frequency of switching between the primary wavelengths by the light valve should be sufficiently rapid to render discrete primary states indistinguishable to the human eye. Two factors dictate the minimum frequency necessary for switching.
The first factor is the ability of the human eye to detect the discrete primary colors (e.g., red, green, blue). At slower than ideal switching speeds, the human eye will detect a flicker and the primaries may not blend.
The second factor determining the frequency of switching is the video refresh rate. During display of video images, the individual frames must be refreshed at frequencies undetectable to the human eye.
The net frequency of switching demanded by the combination of sequential color blending and video refreshing is beyond the capabilities of light valves that utilize thick (>1 &mgr;m) liquid crystal (LC) transducers. However, thin (<1 &mgr;m) liquid crystal transducers have been successfully fabricated. These thin LC transducers demonstrate adequate color sequential blending at video refresh rates. One example of such a thin LC transducer pixel cell structure is disclosed in U.S. Pat. No. 5,706,067 to Colgan et al.
In general, the conventional thin LC transducer pixel cells possess enhanced responsiveness due to the decreased volume of liquid crystal material between the top and bottom plates. A smaller volume enables the liquid crystal to shift orientation more quickly and in response to a lower applied voltage.
FIG. 1
shows a cross-sectional view of a adjacent pixels of a conventional array for a silicon LC light valve. Array portion
100
includes molecules
102
of liquid crystal (LC) sandwiched between a top plate
104
and a bottom plate
106
. Top plate
104
includes a translucent substrate
108
, typically glass or plastic, having an underside coating of a transparent, electrically conducting material that forms passive pixel electrode
109
.
Bottom plate
106
is formed by the reflective surfaces of the pixel electrodes
112
a
and
112
b
. Active electrodes
112
a
and
112
b
, and passive electrode
109
, are coated with first and second alignment layers
111
b
and
111
a
respectively. Alignment layers
111
a-b
(typically composed of polyimide) provide an anchoring surface for ends
102
a
of the LC material
102
interposed between the active pixel electrode and the passive pixel electrode. Alignment layers
111
a-b
are typically scored in order to ensure that LC material
102
is aligned in a particular direction in response to an applied electric field.
The bottom plate
106
is formed by the active reflective metal pixel electrodes
112
a
and
112
b
of adjacent pixels
110
a
and
110
b
, respectively. Pixel electrodes
112
a
and
112
b
are separated and electrically isolated by trenches
118
in inter-pixel regions
119
.
Pixel electrodes
112
a
and
112
b
lie on top of an upper intermetal dielectric layer
128
that forms a component of interconnect scheme
104
. Interconnect
104
overlies capacitor structures
120
a
and
120
b
formed within underlying silicon substrate
105
. Capacitor structure
120
a
includes a dielectric layer
162
formed over a double diffused drain (DDD) region
160
created within silicon substrate
105
. Capacitor structure
120
a
further includes a polysilicon contact component
164
formed over dielectric layer
162
.
Storage capacitors
120
a
and
120
b
are in electrical communication with pixel electrodes
112
a
and
112
b
, respectively, through metal via plugs
140
, middle interconnect metallization layer
124
, and lower interconnect metallization layer
122
. Storage capacitors
120
a
and
120
b
are controlled by MOS switching transistors
142
a
and
142
b
, respectively. MOS switching transistors
142
a
and
142
b
are also formed in underlying silicon substrate
105
, and are electrically isolated from adjacent semiconducting devices by trench isolation structures
144
.
FIGS. 2A-2F
illustrate cross-sectional views of the process for forming the conventional thin LC transducer pixel cell shown in FIG.
1
.
FIG. 2A
illustrates the starting point for the conventional process. Starting structure
200
is created by forming an upper intermetal dielectric layer
128
over a lower interconnect metallization layer (not shown). Portions of upper intermetal dielectric layer
128
corresponding to the center of future pixel regions are then etched to stop on the lower interconnect metallization layer, forming vias. These vias are then filled with electrically conducting material to create via plugs
140
, and then the electrically conducting material is removed outside of the vias.
Next, reflective metal electrode layer
112
is formed over upper intermetal dielectric layer
128
and the tops of via plugs
140
. Photoresist mask
150
is then patterned over reflective metal electrode layer
112
to expose inter-pixel regions
119
.
FIG. 2B
shows etching of reflective metal electrode layer
112
in unmasked inter-pixel regions
119
selective to upper intermetal dielectric layer
128
, defining discrete reflective pixel electrodes
112
a
and
112
b
separated by trench
118
. Photoresist mask
150
is then removed.
At this point in the process flow, the chip upon which the pixel array is being formed is transferred from a conventional silicon processing facility to a one that specializes in the handling of liquid crystal material. Prior to introduction of liquid crystal material to the pixel array, a surface must be formed over the active and passive electrodes that permits uniform alignment of liquid crystal material within the cell.
Accordingly,
FIG. 2C
shows the flowing of a quantity of alignment material
111
over the entire surface, including on top of active reflective pixel electrodes
112
a
and
112
b
, and within trench
118
. Alignment material
111
is typically formed from polyamic acid, water, and a solvent which is spun onto the wafer in liquid form.
FIG. 2D
shows the curing of alignment material
111
, during which solvent is removed and alignment material
111
shrinks and hardens to form alignment layer
111
b
conforming to raised active pixel electrodes
112
a
and
112
b
. As shown in
FIG. 2D
, once alignment layer
111
b
has solidified, the thickness of this layer is non-uniform over the surface of active pixel electrodes. Alignment layer
111
b
includes a thick portion
111
c
at the center of the active pixel electrodes
112
a
and
112
b.
At this point in the process flow, alignment layer
111
b
is scored by a rubbing wheel, which traverses the surface of the pixel cell and gouges alignment layer
111
b
in a uniform direction.
FIG. 2E
shows completion of assembly of the pixel cell by disposing LC material
102
over the active pixel electrodes
112
a
and
112
b
, and then sealing top plate
104
including passive pixel electrode
109
and first alignment layer
111
a
over LC

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