Process for forming semiconductor device with thick and thin...

Details Process for forming semiconductor device with thick and thin... Process for forming semiconductor device with thick and thin...

1999-02-22

2001-07-17

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Utilizing varying dielectric thickness

C438S224000, C438S228000, C438S275000

Reexamination Certificate

active

06261978

ABSTRACT:

FIELD OF THE INVENTION
This invention relates in general to processes for forming semiconductor devices, and more particularly to processes for forming semiconductor devices including gate dielectric layers.
RELATED ART
Semiconductor devices having more than one gate dielectric thickness are becoming more common as transistors operating at different voltage potentials continue to be incorporated into integrated circuit designs. For example, separate transistors in a nonvolatile memory can operate at different voltage potentials to accommodate different power consumption and performance considerations.
The manufacture of devices having different gate dielectric thicknesses can be problematic. One conventional method for forming such devices includes forming a first gate dielectric layer, typically having a thickness greater than approximately 25 nanometers (nm), over the semiconductor device substrate. The first gate dielectric layer is patterned and etched to expose regions of the substrate where a second gate dielectric layer is subsequently formed. After removing the resist, prior to forming the second gate dielectric layer, a preclean sequence is performed. Conventional preclean sequences typically use hydrofluoric (HF) acid solutions, or other oxide etchants, to etch and remove upper portions of the first gate dielectric layer that can contain residual organic mobile ion contamination introduced by the resist layer. Following the preclean step, the second gate dielectric layer, with a thickness typically in a range of approximately 7-10 nm, is formed.
Problems associated with this preclean sequence are related to the uniformity of the etch that removes the uppermost portions of the first gate dielectric layer. For gate dielectric layers below 25 nm, the nonuniformity of the etch produces a varying thickness of gate dielectric layer that results in relatively wide distributions of device parameters, such as charge to breakdown, threshold voltage, and drive currents. In addition, the etch can form pinholes and roughen the surface of the first gate dielectric layer. Surface roughness and pinholes become increasingly detrimental to transistor operation as the gate dielectric layer becomes thinner.
Other methods for forming more than one thickness of gate dielectric layer address these issues. However, they are undesirable for one or more reasons. One such method implants and anneals nitrogen in areas where the thinner gate dielectric layer is to be formed. However, process control and scalability of this method is difficult because the oxidation rate varies significantly depending on the implant conditions. Another method uses a double gate integration process to first form the thinner gate dielectric layer and its electrode before forming the thicker gate dielectric layer. This process is more complex and costly because an additional masking operation is required. In a final method, a thin nitride layer is formed over the first gate dielectric layer to protect it during the HF preclean. However, because the thickness requirement of the nitride layer is only approximately 1-3 nm, conventional furnace nitride depositions cannot be used. The deposition, therefore, requires using lower throughput single wafer processes.


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