Fishing – trapping – and vermin destroying
Patent
1991-06-25
1992-10-20
Thomas, Tom
Fishing, trapping, and vermin destroying
437 47, 437 48, 437 60, 437228, 437233, 437919, H01L 2170
Patent
active
051569922
ABSTRACT:
A memory cell comprises a semiconductor pillar and an insulator on a sidewall of the pillar. A conductive capacitor of the memory cell comprises a first electrode adjacent the insulator. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region coupled to the first electrode.
REFERENCES:
patent: 4672410 (1987-06-01), Miura et al.
patent: 4786954 (1988-11-01), Morie et al.
patent: 4830978 (1989-05-01), Teng et al.
patent: 4873560 (1989-10-01), Sunami et al.
patent: 5027173 (1991-06-01), Satoh
patent: 5034787 (1991-07-01), Dhong et al.
"A Surrounding Gate Transistor (SGT) Cell for 64/256 Mbit DRAMs," by Sunouchi et al., ULSI Research Center, Japan, 1989 IEEE pp. 23-26.
Doering Robert R.
Teng Clarence W.
Barndt B. Peter
Donaldson Richard L.
Matsil Ira S.
Texas Instruments Incorporated
Thomas Tom
LandOfFree
Process for forming poly-sheet pillar transistor DRAM cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for forming poly-sheet pillar transistor DRAM cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming poly-sheet pillar transistor DRAM cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-191811