Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Patent
1982-07-12
1984-03-20
Smith, John D.
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
427 94, 427 95, H01L 21316, H01L 21318
Patent
active
044381573
ABSTRACT:
A process for forming memory quality silicon dioxide and silicon nitride dual-dielectric structures in the same LPCVD furnace system by: forming the silicon dioxide at atmospheric pressure at a temperature of 700.degree.-850.degree. using dry oxygen; heat treating the silicon dioxide layer in ammonia; and forming silicon nitride at 400-600 millitorr and 700.degree.-850.degree. C. using dichlorosilane and ammonia. Optionally, a dielectric layer of silicon oxynitride can be formed on the oxide by using N.sub.2 O, ammonia and dichlorosilane obtaining a memory device with improved retention and endurance.
REFERENCES:
patent: 3924024 (1975-12-01), Naber et al.
patent: 4151537 (1976-04-01), Goldman et al.
patent: 4279947 (1981-07-01), Goldman et al.
W. Kern et al., "Advances in Deposition Processes for Passivation Films", J. Vac. Sci. Tech., vol. 14, No. 5, Sep./Oct. 1977, pp. 1082-1099.
A. Bhattacharyya, "FET Gate Structure for Nonvolatile N-Channel Read-Mostly Memory Device", IBM Tech. Discl. Bull., vol. 18, Nov. 1975, p. 1768.
P. Chen, "Threshold-Alterable Si-Gate MOS Devices", IEEE Trans. on El. Devices, vol. ED-24, No. 5, May 1977, pp. 584-586.
Cavender J. T.
Coca T. Rao
NCR Corporation
Salys Casimer K.
Smith John D.
LandOfFree
Process for forming MNOS dual dielectric structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for forming MNOS dual dielectric structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming MNOS dual dielectric structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1604247