Process for forming isolation regions in an integrated circuit

Details Process for forming isolation regions in an integrated circuit Process for forming isolation regions in an integrated circuit

1996-03-22

1998-06-09

Fourson, George R.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

438496, H01L 2176

Patent

active

057633142

ABSTRACT:
A process for forming isolated active device regions on a silicon substrate comprises the steps of forming at least one trench in a silicon substrate to define at least two active device regions on the substrate to be isolated from each other, depositing an electrically insulative material on the substrate to fill the trench with the material, planarizing the surface of the substrate, performing a masking and etching operation to expose at least one active device region on the substrate, selectively growing a first epitaxial layer of silicon on the exposed active device region, masking the substrate to leave exposed at least one other active device region on the substrate, selectively growing a second epitaxial layer of silicon on the other exposed active device region, the first epitaxial layer and second epitaxial layer being doped with dopant atoms to the same or different dopant concentration to provide at least two isolated active device regions on the silicon substrate. The process of the invention enables the fabrication of performance optimized MOS-type and bipolar devices simultaneously and independently of each other on a single clip or wafer.

Affiliated with

Also associated with

Rating

Process for forming isolation regions in an integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for forming isolation regions in an integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming isolation regions in an integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2198456