Process for forming high and low voltage CMOS transistors on a s

Details Process for forming high and low voltage CMOS transistors on a s Process for forming high and low voltage CMOS transistors on a s

1989-03-17

1991-09-10

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 44, 437 57, 357 42, H01L 21265

Patent

active

050473581

ABSTRACT:
A process for forming both low voltage CMOS transistors and high voltage CMOS transistors on a common integrated circuit chip uses a common implantation and drive-in step to form both the n-type well of each PMOS transistor and the n-type drain extension well of each lightly doped drain (LDD) NMOS transistor and a separate implant and drive-in to form the p-type drain extension well of each LDD PMOS transistor.

REFERENCES:
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M. D. Hartranft et al., "An Integrable 60 Volt A.C. Power MOSFET," Proceedings of Custom Integrated Circuits Conference, Aug. 1980 (copy available from IEEE).
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S. Ogura et al., "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate FIeld-Effect Transistor," IEEE Transaction of Electron Devices, vol. ED-27, No. 8, pp. 1359-1367 (Aug. 1980).
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