Process for forming field isolation structure with minimized enc

Details Process for forming field isolation structure with minimized enc Process for forming field isolation structure with minimized enc

1996-08-19

1997-11-11

Fourson, George

Fishing, trapping, and vermin destroying

H01L 2176

Patent

active

056863489

ABSTRACT:
A method for minimizing the impurity encroachment effect of the field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a first layer and a second layer are deposited on a laminate comprising a substrate having thereon the stacked layers. A photo-resist mask which defines the isolation regions is then formed and the unmasked portion is removed. A third layer is deposited and then is etched anisotropically to form the spacers. A fourth layer is deposited and the chemical-mechanical polishing (CMP) method is applied until the first layer is exposed. After the first layer is removed, the channel-stop ions are implanted, and the spacers are removed for forming the isolation regions by the oxidation. As a result, the channel stop region is self-aligned to the resulting field oxide and the isolation structure is free of the impurity encroachment effect.

REFERENCES:
patent: 4829019 (1989-05-01), Mitchell et al.
patent: 5105829 (1992-04-01), Shida
patent: 5208181 (1993-05-01), Chi
patent: 5286672 (1994-02-01), Hodges et al.
patent: 5432118 (1995-07-01), Orlowski et al.

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