Process for forming device isolation region

Details Process for forming device isolation region Process for forming device isolation region

2000-04-11

2001-11-27

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S221000, C438S427000, C257S508000

Reexamination Certificate

active

06323107

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for forming a device isolation region of a trench structure.
2. Related Art
With reference to FIGS.
5
(
a
) to
8
, a conventional device isolation technique utilizing shallow trenches will be explained hereinbelow.
First, as shown in FIG.
5
(
a
), a pad oxide film
12
of 50 to 200 Å thick and a silicon nitride film
13
of 1000 to 2000 Å thick are formed on a silicon substrate
11
. Then, a resist pattern is formed to cover an active region by a lithography process. Using the resist pattern as a mask, the silicon nitride film
13
and the pad oxide film
12
in a region for forming a device isolation region are removed by dry etching. Then, a trench is formed in the silicon substrate
11
by dry etching as shown in FIG.
5
(
b
).
Then, as shown in FIG.
5
(
c
), the bottom and the sides of the trench formed in the silicon substrate
11
are oxidized by a thickness of 50 to 500 Å at a temperature of 900 to 1100° C. By the oxidization, an opening of the trench in the silicon substrate
11
is rounded and the sides and the bottom of the silicon substrate
11
are covered with a protective film
14
of a silicon oxide film. Then, as shown in FIG.
6
(
a
), an oxide film
15
is deposited by CVD to completely fill the trench. Then, as shown in FIG.
6
(
b
), the buried oxide film
15
is flattened by chemical mechanical polishing. Next, the silicon nitride film
13
and the pad oxide film
12
are removed as shown in FIG.
6
(
c
). A gate oxide film
16
is formed, and a gate electrode material
17
is deposited thereon as seen in FIG.
7
(
a
) and patterned into a gate electrode
17
a
by lithography and dry etching.
According to the above-described process, an edge of the opening of the trench formed in the silicon substrate
11
(indicated by “a” in
FIG. 8
) takes a sharp and almost right-angled form. The edge of the trench opening is optimized by oxidizing the edge in a certain oxidizing atmosphere at a certain oxidizing temperature after the formation of the trench so that the edge “a” is rounded. Further, the oxidization forms the protective film
14
of a silicon oxide film on the surface of the trench. After the later chemical mechanical polishing, the thickness of the flattened buried oxide film
15
filled in the trench is reduced by removal of the silicon nitride film
13
and the pad oxide film
12
. As a result, a top portion of the buried oxide film in the device isolation region becomes lower than the surface of the silicon substrate in the active region as shown in FIG.
6
(
c
).
When the gate oxide film and the gate electrode are formed thereafter, a channel region at a final stage extends to include the edge of the trench opening as shown in FIG.
7
(
b
). Accordingly, if the edge is not sufficiently rounded, a gate electric field strengthens at this portion when a MOS transistor is operated and the transistor assumes apparent characteristics as if parasitic MOS transistors having much lower threshold value are arranged in parallel. Further, in a non-volatile memory utilizing the gate oxide film
16
as a tunnel oxide film, an F-N tunneling electric field increases in the edge region. Therefore an F-N tunneling current increases locally, and reliability in rewriting the non-volatile memory is deteriorated. Further, a thickness of the gate oxide film is reduced in the region where the edge is not sufficiently rounded, which further accelerates the above problem.
Further, in the above process, the optimization of the edge of the trench opening needs to be performed in one oxidization after the trench is formed. Therefore, to oxidize the edge for better roundness, the edge must be oxidized to a greater extent in one time. However, in case where the oxidization is performed after a certain amount of the oxide film has been formed, the silicon oxide film formed by oxidizing silicon increases in volume, which causes internal stress to accumulate in the edge region of the trench opening. Therefore, it is problematic because the device characteristics are adversely affected, the profile of the edge is varied due to a remarkable increase of the stress immediately after the oxidization or variations in the profile are increased.
SUMMARY OF THE INVENTION
The present invention is intended to improve flexibility to control the curvature of the edge region of the trench opening provided in the silicon substrate which also serves as an edge portion of an active region, alleviate the stress concentrated on the region and reduce heat hysteresis necessary to obtain a desired profile of the edge region.
According to the present invention, provided is a process for forming a device isolation region comprising the steps of: forming a pad oxide film and a silicon nitride film on a semiconductor substrate; removing the pad oxide film and the silicon nitride film on a region for device isolation and forming a trench in the semiconductor substrate by etching using the remaining pad oxide film and silicon nitride film as an etching mask; forming a first oxide film on the bottom and sidewalls of the trench and below the pad oxide film under an end portion of the silicon nitride film using the silicon nitride film as a mask resistant to oxidization; forming a gap between the silicon nitride film and the semiconductor substrate by removing the first oxide film on the bottom and the sidewalls of the trench and the first oxide film and the pad oxide film below the end portion of the silicon nitride film by etching using the silicon nitride film as an etching mask; forming a second oxide film at least on the bottom and the sidewalls of the trench and in the gap using the silicon nitride film as a mask resistant to oxidization; and forming a third oxide film so as to fill the trench, thereby to form a device isolation region.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.


REFERENCES:
patent: 5258332 (1993-11-01), Horioka et al.
patent: 5863827 (1999-01-01), Joyner
patent: 5880004 (1999-03-01), Ho
patent: 6054343 (2000-04-01), Ashburn
patent: 6074932 (2000-06-01), Wu
patent: 6103635 (2000-08-01), Chau et al.
patent: 10-12716 (1996-08-01), None
M. Nandakumar et al. “Shallow Trench Isolation for advanced ULSI CMOS Technogies” Silicon Technolgy Development, Kilby Center, Texas Instruments. Sep.1998.

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