Process for forming and analyzing stacked die

Details Process for forming and analyzing stacked die Process for forming and analyzing stacked die

2007-07-31

2007-07-31

Coleman, William David (Department: 2823)

Semiconductor device manufacturing: process

With measuring or testing

C324S765010

Reexamination Certificate

active

10873814

ABSTRACT:
In a stacked die integrated circuit structure, the structure can subsequently be tested by removing any packaging material and separating the die from a die paddle and from each other. The separation can involve the use of chemicals or heat, with or without the use of mechanical force. One aspect of the invention includes making use of specifically chosen adhesives to secure the die to the die paddle and to each other, so that any subsequent removal can readily be achieved.

REFERENCES:
patent: 5483174 (1996-01-01), Hembree et al.
patent: 6039899 (2000-03-01), Martin et al.
patent: 6245586 (2001-06-01), Colvin
patent: 6331728 (2001-12-01), Chang et al.
patent: 6590409 (2003-07-01), Hsiung et al.
patent: 7112981 (2006-09-01), Gao

Affiliated with

Also associated with

Rating

Process for forming and analyzing stacked die does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for forming and analyzing stacked die, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming and analyzing stacked die will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3795812