Process for forming adjacent moats or holes

Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Treating electrolytic or nonelectrolytic coating after it is...

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205223, 205261, C25D 502, C25D 534

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active

059449764

ABSTRACT:
A process for forming adjacent moats or holes in an electrically non-insulating substrate wherein an electrically insulating masking layer is deposited on the substrate. To form two adjacent moats or holes, the masking layer has an opening whose width is chosen so that it extends over a part of the overall width of the two moats or holes to be formed, and whose shape corresponds to the shape of the moats or holes to be formed. The surface of the masked substrate is then subjected to an anodic oxidation, with the oxidation voltage chosen to be so high that two adjacent moats or holes are formed per opening in the masking layer.

REFERENCES:
patent: 4248683 (1981-02-01), Shaw
patent: 4268348 (1981-05-01), Allison et al.
patent: 5229682 (1993-07-01), Komatsu
Dopant Selective HF Anodic Etching of Silicon for the Realization of Low-Doped Monocrystalline Silicon Microstructures, Nr. Workshop 4, IEEE, Seiten 221-226, Jan. 30, 1991.
Formation Mechanism and Properties of Electrochemically Etched Trenches in N-Type Silicon, J. Electrochem Soc., vol. 137, No. 2, pp. 653-659, Feb. 1990.

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