Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
2000-01-26
2000-11-14
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438427, 438695, H01L 2176
Patent
active
061469718
ABSTRACT:
A method is used to form a shallow trench isolation structure. According to the invention, prior to performing CMP on a HDPCVD oxide layer, a smoothing step is performed on the HDPCVD oxide layer to smooth the peak profile of the oxide layer to reduce the moment resulting from the CMP on the peak, and to prevent the later-formed shallow trench isolation structure from being pulled out. In addition, since the invention prevents the later-formed shallow trench isolation structure from being pulled out, the particles resulting from the oxide pulled out from the shallow trench are reduced. Thus, particle damage to the surface of the wafer is reduced.
REFERENCES:
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5880007 (1999-03-01), Varian et al.
patent: 5981355 (1999-11-01), Lee
patent: 5998279 (1999-12-01), Liaw
Chen Chun-Lung
Hsiao Hsi-Mao
Lee Tzung-Han
Yu Hung-Chen
Dang Trung
Huang Jiawei
United Microelectronics Corp
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