Process for forming a semiconductor device including conductive

Details Process for forming a semiconductor device including conductive Process for forming a semiconductor device including conductive

1995-09-05

1997-01-14

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437195, 437228, 1566361, 1566561, H01L 213213

Patent

active

055939198

ABSTRACT:
The embodiments of the present invention allow the formation of interconnect and vias without forming via veils or excessive thinning of vias. Conductive members (52, 54, 56, 58) are formed with a pattern generally corresponding to the shape of interconnects. A lower intermetallic insulating layer (70)is deposited over the substrate (30) and removed over conductive members (52, 54, 56, 58) before forming via portions. Via portions are formed from the conductive members (52, 54, 56, 58). An upper intermetallic insulating layer (134) is formed and planarized to fill locations overlying the interconnect portions of the conductive members (52, 54, 56, 58) near the vias.

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