Process for forming a self-aligned raised source/drain MOS devic

Details Process for forming a self-aligned raised source/drain MOS devic Process for forming a self-aligned raised source/drain MOS devic

1996-05-28

1998-09-08

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Responsive to non-optical, non-electrical signal

257382, 257412, 257506, 257623, 257742, 257752, 257773, 438184, 438230, 438297, 438300, H01L 2982

Patent

active

058048464

ABSTRACT:
The present invention is directed to a process for forming a self-aligned raised source/drain MOS device comprising a planarized metal layer, preferably tungsten, overlying a source, a drain, and a gate that is provided on both sides with an insulating spacer to electrically isolate it from the source and drain. The planarized tungsten layer comprises a first portion whose lower surface is in contact with a polysilicon layer of the gate. The lower surface of each of the second and third portions of the tungsten layer is in contact with the source and drain, respectively. The second and third portions are insulated from the first portion by the insulating spacers, and the upper surfaces of all the portions comprise a coplanar surface. Planarization of the deposited metal layer thus provides ohmic contact at substantially the same level to the source, drain, and gate. In a self-aligned raised source/drain MOS device formed by the process of the invention, the second and third portions of the planarized metal layer preferably extend laterally over the field oxide and are characterized by an upper:lower surface width ratio of from about 2:1 to 4:1.

REFERENCES:
patent: 4822749 (1989-04-01), Flanner et al.
patent: 4983536 (1991-01-01), Bulat et al.
patent: 5057902 (1991-10-01), Haskell
patent: 5397722 (1995-03-01), Bashir et al.
patent: 5439839 (1995-08-01), Jang
M. Sekine et al., "Self-Aligned Tungsten Strapped Source/Drain and Gate Technology Realizing The Lowest Sheet Resistance For Sub-Quarter Micron CMOS", IEEE, Japan, 1994, pp. 493-496.
W. T. Lynch, "Self-Aligned Contact Schemes For Source-Drains In Submicron Devices", IEEE, New Jersey, 1987, pp. 354-357.
C. K. Lau et al., "A Super Self-Aligned Source/Drain MOSFET", IEEE, California, 1987, pp. 358-361.

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