Process for forming a self-aligned FET having a T-shaped gate st

Details Process for forming a self-aligned FET having a T-shaped gate st Process for forming a self-aligned FET having a T-shaped gate st

1989-09-05

1991-03-05

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 44, 437187, 437203, 437912, 148DIG100, H01L 2128

Patent

active

049977784

ABSTRACT:
A process for formation of a GaAs MESFET for use in digital IC and MMIC is disclosed, the MESFET having a high operating speed and low noise characteristics. A multilayer resist comprising a nitride film, a photo resist, a titanium deposition layer, and a SiO layer made by SOG (spin-on-glass) is formed, and a gate which is formed in the length of 0.7-1 .mu.m by applying the photo transfer method is transcribed in the length of 0.3-0.5 .mu.m. The pattern of the gate is transcribed by etching it down to GaAs, and the place for the positioning of the T-shaped gate is defined by depositing tungsten silicide and by side-etching the photo resist. The T-shaped gate is manufactured by electroplating gold, and by lifting off the rest of the portions. The source and drain are then formed in a self-aligned manner by ion-implanting to a high concentration, and then a heat treatment is carried out to make active. A resistant contact is then formed by applying the photo transfer method and an etching, and is completed by depositing AuGe/Ni and by carrying out an alloy-treatment. A conventional metallization is then performed to complete the self-aligned gaAs MESFET having a T-shaped gate.

REFERENCES:
patent: 4536942 (1985-08-01), Chao et al.
patent: 4551905 (1985-11-01), Chao et al.
patent: 4561169 (1985-12-01), Miyazaki et al.
patent: 4599790 (1986-07-01), Kim et al.
patent: 4728621 (1988-03-01), Graf et al.
patent: 4808545 (1989-02-01), Balasubramanyam

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