Process for forming a polysilicon electrode in a trench

Details Process for forming a polysilicon electrode in a trench Process for forming a polysilicon electrode in a trench

1995-02-21

1997-08-12

Niebling, John

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

438589, 438243, 438258, 438259, H01L 2144, H01L 2148

Patent

active

056565445

ABSTRACT:
A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.

REFERENCES:
patent: 4471471 (1984-09-01), DiMaria
patent: 4728623 (1988-03-01), Lu et al.
patent: 4929988 (1990-05-01), Yoshikawa
patent: 4990979 (1991-02-01), Otto
patent: 5017977 (1991-05-01), Richardson
patent: 5020030 (1991-05-01), Huber
patent: 5049956 (1991-09-01), Yoshida et al.
patent: 5053842 (1991-10-01), Kojima
patent: 5468663 (1995-11-01), Bertin et al.
"A 4M Bit NVRAM Technology Using a Novel Stacked Capacitor On Selectively Self-Aligned Flotox Cell Structure" I.E.D.M. 90. 931-933 (1990).

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