Process for forming a nonvolatile random access memory array

Details Process for forming a nonvolatile random access memory array Process for forming a nonvolatile random access memory array

1995-02-27

1996-10-22

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 60, 437195, H01L 218242

Patent

active

055676367

ABSTRACT:
An NVRAM array (30) has a portion (31) associated with a drive line segment (DSL.sub.11). The drive line segment (DSL.sub.11) is coupled to a drive line (DL1) by a control transistor (32). The layout allows a conductive member (112) that is part of lo the drive line segment (DSL.sub.11) to be formed at about the same elevation as the memory capacitors (118). The layout further allows interconnects (136) for the drive lines (DL1, DL.sub.2) and bit lines (BL.sub.11, BL.sub.12, BL.sub.13, BL.sub.14) to be formed over the control and memory transistors (32, 34), as opposed to between the transistors. The process forms a small and reliable NVRAM device.

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patent: 5439840 (1995-08-01), Jones, Jr. et al.

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