Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Patent
1999-08-05
2000-02-08
Graybill, David E.
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
438599, 438611, 438623, H01L 2156, H01L 2160
Patent
active
060227621
ABSTRACT:
A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material includes formation above an intermediate process structure of a dielectric multilayer comprising a layer of amorphous planarizing material. The process also includes the partial removal of the dielectric multilayer so as to create at least one peripheral termination of the multilayer in the device edge morphological structure. Removal of the dielectric multilayer requires that the peripheral termination thereof be located in a zone of the intermediate process structure relatively higher than the level of the major surface, if compared with adjacent zones of the intermediate structure itself at least internally toward the circuit and in so far as to the device edge morphological structure.
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Galanthay Theodore E.
Graybill David E.
STMicroelectronics S.r.l.
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