Process for forming a low resistance interconnect in MOS N-chann

Details Process for forming a low resistance interconnect in MOS N-chann Process for forming a low resistance interconnect in MOS N-chann

1976-02-10

1977-03-22

Rutledge, L. Dewayne

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29571, 29578, 29589, 148 15, 148187, 148188, 357 23, 357 41, 357 51, 357 59, 427 86, 427 85, H01L 21225, H01L 2120, H01L 2702

Patent

active

040134890

ABSTRACT:
A low resistance crossunder (interconnect) for n-channel, silicon gate integrated circuits, particularly useful where shallow source and drain regions are employed. The crossunder is formed in the substrate from a doped polycrystalline silicon layer which contacts the substrate at the site of the crossunder. The crossunder is formed without substantial alterations to the standard process flow.

REFERENCES:
patent: 3519901 (1970-07-01), Bean et al.
patent: 3699646 (1972-10-01), Vadasz
patent: 3747200 (1973-07-01), Rutledge
patent: 3750268 (1973-08-01), Wang
patent: 3775191 (1973-11-01), McQuhae
patent: 3843425 (1974-10-01), Katnack
patent: 3904450 (1975-09-01), Evans et al.
Bassous, E., "Fabricating Submicrometer Silicon Devices", I.B.M. Tech. Discl. Bull., vol. 15, No. 6, Nov. 1972, pp. 1823-1825.

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