Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of...
Reexamination Certificate
1999-11-18
2001-11-06
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
C438S510000, C438S318000, C438S353000, C438S357000, C438S358000, C438S363000, C438S355000, C438S359000, C438S416000, C438S418000, C438S426000
Reexamination Certificate
active
06313000
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for forming a transistor device, and in particular, to a process for forming a vertically isolated bipolar transistor having a doped isolation region constrained by a trench.
2. Description of the Related Art
FIG. 1A
shows a plan view of a conventional vertically-isolated PNP bipolar transistor
100
formed in P-type silicon substrate
102
and overlying P-type epitaxial silicon
164
.
FIG. 1B
shows a cross-sectional view of the transistor of
FIG. 1A
along the line
1
B-
1
B′.
PNP transistor
100
comprises N-type base region
104
formed in P-type collector region
106
. P-type emitter region
108
is formed within base
104
. Collector region
106
of bipolar transistor
100
is in electrical contact with heavily doped buried P-type layer
110
. Electrical contact to buried P-type layer
110
is permitted through P-type sinker
112
. Electrical contact with emitter
108
is permitted through polysilicon emitter contact structure
114
. Polysilicon emitter contact structure
114
is separated from base region
104
by dielectric
116
.
Lateral electrical isolation of PNP transistor
100
from adjacent devices is accomplished by trench isolation structure
118
comprising surface LOCOS isolation
120
overlying polysilicon-filled deep trench
122
.
Because collector
106
of bipolar transistor
100
is P-type silicon, collector
106
must be electronically isolated from underlying P-type substrate
102
in which adjacent devices are formed. Therefore, vertical isolation of PNP bipolar transistor
100
is accomplished by underlying N-type isolation region
124
. Electrical contact with isolation region
124
is enabled by N-type sinker
126
.
FIGS. 2A-2G
show cross-sectional views of a conventional process flow for forming the bipolar transistor of
FIGS. 1A-1B
.
FIG. 2A
shows the starting point of the process, wherein first photoresist mask
250
is patterned over P-type single crystal silicon substrate
202
, and N-type dopant is implanted into unmasked region
252
to form implanted N-isolation region
254
. In the example shown in
FIGS. 2A-2G
, implanted N-isolation region
254
is a square 10 &mgr;m×10 &mgr;m region having a depth of 0.2 &mgr;m.
FIG. 2B
shows the next step in the process, wherein the first photoresist mask is stripped, and P-type silicon substrate
202
is heated to drive implanted N-type dopant into substrate
202
. Thermal diffusion of dopant associated with the heating shown in
FIG. 2B
causes implanted N-isolation region
254
to spread both laterally and vertically to form a 30 &mgr;m×30 &mgr;m diffused N-isolation region
224
having a depth of 10 &mgr;m. As will be discussed at length, this thermal diffusion step undesirably increases the size of the bipolar device and thereby reduces packing density.
FIG. 2C
shows the next step, wherein second photoresist mask
258
is patterned over P-type substrate
202
, and P-type dopant is implanted into unmasked region
260
to form “buried” P-type layer
210
.
FIG. 2D
shows that P-type layer
210
is “buried” by P-type epitaxial silicon
264
subsequently created over P-type substrate
202
, forming P-type collector
206
.
In
FIG. 2E
, additional photoresist masks (not shown) are successively patterned. P-type dopant
266
is implanted into single crystal silicon to form precursor P-type collector sinker
268
, and N-type dopant
270
is implanted into single crystal silicon to form precursor N-isolation sinker
272
.
FIG. 2F
shows patterning of third photoresist mask
274
, followed by etching of epitaxial silicon
264
and underlying silicon substrate
202
in unmasked regions
274
to form deep trenches
222
. Deep trenches
222
extend to a depth into substrate
202
below buried P-type layer
210
.
FIG. 2G
shows a second thermal drive-in step, wherein the silicon is heated to drive the N- and P-type sinker dopant further into the single crystal silicon. As a result of the thermal diffusion of dopant, the precursor P-type collector sinker is transformed into P-type collector sinker
212
contacting buried P-type layer
210
. Precursor N-isolation sinker is transformed into N-isolation sinker
226
contacting N-isolation region
224
.
FIG. 2G
also shows the filling of deep trenches
222
with polysilicon, followed by formation of surface LOCOS structures
220
overlying polysilicon-filled deep trenches
222
.
Completion of fabrication of the bipolar device of
FIGS. 1A and 1B
is accomplished by conventional processes.
While the conventional process flow for forming the PNP bipolar transistor is suitable for many applications, the process suffers from a serious disadvantage. Specifically, formation of the N-isolation region by ion-implantation followed by thermal drive-in (as depicted in
FIGS. 2A-2B
) produces an N-isolation region having lateral dimensions much greater than is necessary to accomplish vertical isolation.
For example, in
FIG. 1A
diffused N-isolation region
124
is a square having dimensions of 30 &mgr;m×30 &mgr;m, yielding a total device area of about 1000 &mgr;m
2
. This N-isolation area is excessively large to afford vertical isolation, and the surface area occupied by the isolation region undesirably lowers permissible packing density of the bipolar devices.
Therefore, there is a need in the art for a process for forming a vertically-isolated bipolar transistor permitting greater device packing density than conventional processes.
SUMMARY OF THE INVENTION
The present invention proposes a process flow for forming a vertically-isolated bipolar transistor in which the area occupied by the isolation region is constrained by prior formation of a trench. Specifically, a first trench is etched in the substrate to circumscribe a silicon area expected to be occupied by active device regions. Dopant providing vertical isolation is then implanted and thermally driven into the silicon. The implanted isolation dopant diffuses vertically into the substrate, but lateral expansion is prevented by the trenches. In this manner, a bipolar transistor device having substantially reduced lateral dimensions is fabricated, thereby enabling increased device packing density.
An embodiment of a process flow for forming a bipolar transistor in accordance with the present invention comprises the steps of forming a first trench in a semiconductor workpiece of a first conductivity type, the first trench circumscribing a precursor device region, and filling the first trench with a sacrificial material. Conductivity-altering dopant of a second conductivity type opposite to the first conductivity type is introduced into the precursor device region and caused to diffuse in a vertical direction into the semiconductor workpiece, the first trench constraining lateral diffusion within the semiconductor workpiece of the conductivity-altering dopant of the second type. A second trench is formed in the semiconductor workpiece, the second trench broader than and encompassing the first trench, such that the sacrificial material is consumed. The second trench is filled with a dielectric material. A collector of the first conductivity type is formed within the precursor device region. A base of the second conductivity type is formed within the collector, and an emitter of the first conductivity type is formed within the base.
An embodiment of a method of constraining lateral diffusion of conductivity-altering dopant within a semiconductor workpiece during a thermal drive-in step comprises the steps of circumscribing a precursor doped region of the semiconductor workpiece with a first trench, introducing conductivity-altering dopant into the precursor doped region, and applying thermal energy to drive the dopant into the semiconductor workpiece after formation of the first trench, such that the first trench blocks lateral diffusion of the conductivity-altering dopant.
The features and advantages of the present invention will be understood upon consideration of the following detailed descrip
Keshavan B. V.
National Semiconductor Corporation
Smith Matthew
Stallman & Pollack LLP
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