Process for filling submicron spaces with dielectric

Details Process for filling submicron spaces with dielectric Process for filling submicron spaces with dielectric

1992-07-21

1993-12-14

Fourson, George

Fishing, trapping, and vermin destroying

437238, 437245, 148DIG158, 20419232, 20419237, H01L 21465

Patent

active

052702642

ABSTRACT:
A process for filling submicron, high aspect ratio gaps, that may have reentrant angles, with a high quality ILD. A first ILD layer is deposited using PECVD to partially fill the gap. Medium-pressure sputter etching is then used to remove the bread-loaf edges and redeposit the etched material in the gaps, thereby allowing small gaps with high aspect ratios and reentrant angles to be completely filled. Finally, a second ILD layer that completely fills the gap is deposited using PECVD.

REFERENCES:
patent: 3617463 (1971-11-01), Gregor et al.
Valletta, R., "Control of Edge Profile in Sputter Etching", IBM Technical Disclosure Bulletin, vol. 10, No. 12 May 1968.
Kotani, H., et al, "Sputter Etching . . . Metallization", J. Electrochem. Soc. & Solid State Science & Tech., Mar. 1983 pp. 645-648.
Vossen, J., et al, "Back Scattering . . . Targets", RCA Review, Jun. 1970, vol. 31, No. 2, pp. 293-305.
Wolf, S. et al, Silicon Processing for the VLSI Era; vol. 1, Process Technology, Lattice Press, 1986 pp. 343-344.

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