Process for filling polysilicon seam

Details Process for filling polysilicon seam Process for filling polysilicon seam

2003-02-27

2004-09-14

Kielin, Erik J. (Department: 2813)

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

Reexamination Certificate

active

06790740

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for filling a polysilicon seam, and more particularly to a process for filling a polysilicon seam in trench capacitor fabrication.
2. Description of the Prior Art
Presently, the density of dynamic random access memory (DRAM) increases continuously. It is thus necessary to decrease the memory cell size and maintain adequate storage capacitance to normally operate DRAM. Therefore, in recent years, trench capacitors have been extensively used in DRAM. A trench capacitor includes a trench in a substrate and n
+
-doped polysilicon filled in the trench to serve as an electrode plate for the capacitor. The n
+
-dopant is diffused into the substrate beneath the trench bottom to form another electrode plate, referred to as a buried plate. A dielectric layer is disposed between these two plates, making up a trench capacitor.
FIGS. 1
a
to
1
c
are cross-sections illustrating the conventional process flow of fabricating a trench capacitor with greater design rule (for example, about 0.25 &mgr;m). First, referring to
FIG. 1
a
, a pad oxide layer
112
is formed on a semiconducting substrate
100
by thermal oxidation. Then, a silicon nitride layer
114
is formed by chemical vapor deposition (CVD). Then, a BSG (boron silicate glass) layer (not shown) is formed by CVD. Then, photolithographic and etching techniques are performed to form patterned pad oxide layer
112
, patterned silicon nitride layer
114
, and patterned BSG layer. Then, the semiconducting substrate
100
uncovered by the BSG layer is etched downwardly, forming a trench
116
with a predetermined depth, for example, 6-8 &mgr;m.
Subsequently, referring to
FIG. 1
b
, a silicon nitride layer
200
is formed on the inner wall of the trench
116
and on the surface of the substrate
100
. Then, a polysilicon layer
300
is formed to fill the trench
116
. Due to the width restriction of the trench
116
, it is very difficult for the polysilicon layer
300
to enter into the bottom of the trench
116
. Thus, a seam
400
is formed at a position below a depth h
1
(generally about 3 &mgr;m) from the surface of the substrate
100
. Thus far, the semiconducting substrate
100
, the dielectric layer
200
, and the polysilicon layer
300
collectively make up the trench capacitor.
Subsequently, referring to
FIG. 1
c
, the polysilicon layer
300
is etched back to a predetermined depth. Then, the silicon nitride layer
200
is removed by wet etching to leave a polysilicon layer
320
and a silicon nitride layer
220
, which have a distance H (generally controlled to 1.5 &mgr;m) from the substrate
100
surface. The trench is divided into a top portion I where there is no polysilicon
320
, and a bottom portion II where polysilicon
320
exists. The bottom portion II makes up a trench capacitor. In the top portion I, the substrate
100
is exposed to connect the trench capacitor to outer conducting lines. Since the seam
400
is located at a deep position and h
1
is far greater than H, the seam
400
is not exposed, thus not affecting reliability.
However, when the design rule is decreased, different situations occur.
FIGS. 2
a
to
2
c
are cross-sections illustrating the conventional process flow of fabricating a trench capacitor with smaller design rule, for example, less than 0.125 &mgr;m (sub half-quarter). First, referring to
FIG. 2
a
, a pad oxide layer
112
is formed on a semiconducting substrate
100
by thermal oxidation. Then, a silicon nitride layer
114
is formed by chemical vapor deposition (CVD). Then, a BSG (boron silicate glass) layer (not shown) is formed by CVD. Then, photolithographic and etching techniques are performed to form patterned pad oxide layer
112
, patterned silicon nitride layer
114
, and patterned BSG layer. Then, the semiconducting substrate
100
uncovered by the BSG layer is etched downwardly, forming a trench
120
with a predetermined depth, for example, 6-8 &mgr;m.
Subsequently, referring to
FIG. 2
b
, a silicon nitride layer
250
is formed on the inner wall of the trench
126
and on the surface of the substrate
100
. Then, a polysilicon layer
350
is formed to fill the trench
120
. Please compare
FIGS. 1
b
and
2
b
. In
FIG. 2
b
, since the trench
120
is narrower than trench
116
, it is much more difficult for the polysilicon layer
350
to enter into the bottom of the trench
120
. Thus, the polysilicon layer
350
closes the seam
120
in a very high position and a seam
450
is formed at a position below a depth h
2
(h
2
<h
1
, h
2
is generally less than about 1.5 &mgr;m) from the surface of the substrate
100
. Thus far, the semiconducting substrate
100
, the dielectric layer
250
, and the polysilicon layer
350
collectively make up the trench capacitor.
Subsequently, referring to
FIG. 2
c
, the polysilicon layer
350
is etched back to a predetermined depth. Considering that the top portion of the trench
120
can connect to an outer conducting line, the polysilicon layer
350
must be etched to a position below a depth H (generally about 1.5 &mgr;m) from the surface of the substrate
100
. Since H>h
2
, after etching the polysilicon layer
350
, the seam
450
is exposed. Then, the silicon nitride layer
250
is removed by wet etching. A polysilicon layer
380
and a silicon nitride layer
280
are left in the trench
120
. Since the seam
450
is exposed, reliability problems occur.
SUMMARY OF THE INVENTION
An object of the present invention is to solve the above-mentioned problems and provide a process for filling a polysilicon seam to prevent reliability problems.
To achieve the above object, the present inventive process for filling a polysilicon seam includes the following steps. First, a semiconducting substrate or an insulating layer having a trench is provided, and a first polysilicon layer having a seam is filled in the trench. Next, the first polysilicon layer is etched to expose the seam. Next, a second polysilicon layer is formed to fill the top portion of the seam and close the seam.


REFERENCES:
patent: 5824580 (1998-10-01), Hauf et al.
patent: 6426253 (2002-07-01), Tews et al.
patent: 6559030 (2003-05-01), Doan et al.
patent: 6576565 (2003-06-01), Gluschenkov et al.
patent: 2003/0017675 (2003-01-01), Chen et al.

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