Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-01-11
2001-05-08
Thomas, Tom (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S233000, C257S510000, C136S249000
Reexamination Certificate
active
06229194
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to semiconductor devices and, more specifically, relates to a novel process for fabricating a trench structure for a device in which an array of planar cells are formed in a single silicon wafer and are dielectrically isolated from one another.
It is often desirable to fabricate a semiconductor device formed of large number of cells. Photovoltaic generators (PVG), for example, are well known and are commonly used for producing a control signal for a solid state relay. Such devices employ an LED which is energized by input terminals to irradiate the photosensitive surface of a spaced and insulated photovoltaic device. The output of the photovoltaic device may serve as the input to a switching device, such as a MOS-gated device, typically a power MOSFET or IGBT, which has load terminals which are switched “on” in response to the energization of the LED. The input and output terminals of the relay are isolated by the gap between the LED and the photovoltaic device. Commonly, the photovoltaic device consists of a large number of series-connected photovoltaic cells in order to produce a voltage sufficiently high to turn on the power switching device. Such devices are well known and are sold under the name “PVI” (photovoltaic isolator) by the International Rectifier Corporation of El Segundo, Calif., the assignee of the present invention.
The plural cell photogenerator can be made in many different ways. One known generator employs a stack or pile of photovoltaic cells as shown in U.S. Pat. Nos. 4,755,697 and 4,996,577, both to Daniel M. Kinzer. Other devices employ a planar array of cells which are junction isolated from one another and are connected in series at their surfaces. Still other devices are known in which individual cells disposed over the surface of a silicon chip are junction-isolated from one another or may be dielectrically isolated, as shown in U.S. Pat. Nos. 4,227,098 and 4,390,790. The prior art devices, however, have the drawback of being expensive to manufacture as well as having low manufacturing yields.
Alternatively, a planar array of photovoltaic generating cells are formed in a dielectrically bonded silicon wafer. A relatively thick “handle” wafer is oxide bonded to, as well as insulated from, a thin device wafer in which the junctions are formed, as shown in U.S. Pat. No. 5,549,762 to the present applicant. This device, however, requires a relatively expensive starting wafer.
It is therefore desirable to produce a photovoltaic generator that can be formed of a large number of insulated cells which can be connected in series to produce a turn-on signal for a power MOS-gated device but which is easily manufactured and integrated with the MOS-gated device using existing reliable processing equipment and techniques. More specifically, it is desirable to produce a photovoltaic generator comprised of planar photovoltaic generating cells formed in a single wafer in which the cells are dielectrically isolated by a trench structure in which the trenches are of a predefined depth and are filled with an insulating material to dielectrically insulate each of the cells. The fabrication process for such a device is described, for example, in U.S. application Serial No. (IR-1457), which is incorporated herein by reference.
During the fabrication of such a trench structure, however, the oxide or other dielectric material that is grown or deposited in the trench often is thicker at the upper portion of the trench than in the lower regions of the trench. As a result, the deposited or grown insulating material may pinch-off and close the upper opening of the trench while leaving a lower region in the trench unfilled. The gaps in the trench weaken the insulating properties of the trench and can produce devices with lower voltage ratings as well as poor mechanical properties. This problem is further exacerbated when the trench is etched with the upper part of the walls at a re-entrant angle which produces a “pinch-off” region in which the upper opening of the trench is closed off while leaving a lower region in the trench unfilled.
It is therefore desirable that the fabrication process for the device produce a trench structure in which the trench is completely filled.
BRIEF DESCRIPTION OF THE INVENTION
The present invention provides a novel process for the manufacture of a trench structure that is used to dielectrically isolate the respective cells of a multiple cell semiconductor device formed in a single wafer.
In accordance with the present invention, a masking layer is formed on the top surface of a silicon substrate and is photolithographically patterned and etched. A trench is then etched in the openings in the masking layer, and the masking layer is then removed. An oxide layer is then grown or deposited on the interior walls and on the bottom surface of the trench, and then a dry, anisotropic etch is carried out to remove the oxide from the upper surface of the substrate as well as remove the oxide from the walls of the top portion of the trench. The trench can then be filled with polysilicon. Alternatively, a second, thinner oxide layer can be grown or deposited on the substrate as well as on the trench walls to provide surface and edge protection, and the trench then filled with polysilicon. Any polysilicon that is deposited on the top surface of the substrate is then removed by chemical mechanical polishing.
Other process steps may then be carried out, such as the deposition, patterning and etching of an overlaying insulation layer as well as the deposition, patterning and etching of a conductive layer. Then, the back side of the silicon substrate may be removed until the bottom of the trench is approached or reached. The back side may then be further polished until the trench liner oxide appears on the bottom surface. An insulating passivation may then be deposited on the back surface of the substrate, and a beam support may be used to insure that the trenched, back etched wafer holds together.
In accordance with another aspect of the present invention, the trench is etched in the manner described above but with an opening that is narrower at the top surface than in the lower regions of the trench so that the walls of the trench angle inward at the top surface, namely a re-entrant surface profile. The subsequent dry etching of the first oxide layer also removes this re-entrant structure.
In accordance with the present invention, dielectrically isolated, planar photovoltaic generating cells, which include a trench structure fabricated in the manner described above, are formed in a single wafer and may be integrated with one or more power devices in the same wafer.
A plurality of N+ (or P+) diffusions are formed in a lightly doped P type (or N type) starting wafer and are each enclosed by a ring shaped P+ (or N+) contact diffusion. Individual planar and spaced cells or tubs are then formed by etching an array of intersecting trenches between the P+ (or N+) contact diffusions in the manner of the invention. The trenches extend through the thin device layer to a predefined depth and are then filled with dielectric layers and with polysilicon to dielectrically insulate each of the tubs as described above. The N+ top contact of each cell is connected to the P+ contact of an adjacent cell to connect each of a predetermined number of the cells in series.
The back side of the silicon is then ground off to the level of the bottom of the trenches and polished until the liner oxide is exposed, and an insulating oxide is grown on the back surface. A beam support may be used to insure that the trenched, ground wafer holds together.
An MOS-gated device may be integrated into the same chip as the photovoltaic generator structure in a trenched or an untrenched area of the wafer. The MOS-gated device, which may a lateral or vertical MOSFET or a lateral or vertical IGBT, is formed prior to the grinding of the back side of the wafer and may be formed prior to or subsequent to the formation of
Hu Shouxiang
International Rectifier Corp.
Ostrolenk Faber Gerb & Soffen, LLP
Thomas Tom
LandOfFree
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