Process for fabrication of semiconductors utilizing selectively

Details Process for fabrication of semiconductors utilizing selectively Process for fabrication of semiconductors utilizing selectively

1979-05-02

1980-05-27

Rutledge, L. Dewayne

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29571, 29578, 148187, 148190, 156653, 156657, 156662, 357 23, 357 54, H01L 21225, H01L 21316

Patent

active

042048940

ABSTRACT:
A process for fabrication of semiconductor devices comprising the steps of depositing over the surface of a semiconductor wafer a first insulating layer containing impurities which are to be diffused into the wafer so as to form source and drain regions, depositing a second insulating and melt-flow layer which is softened or melted at low temperatures, opening contact windows, forming a third insulating layer which also contains impurities to be diffused into the wafer so as to form source drain regions, subjecting the wafer to a heat treatment so as to cause melt-flow and form source and drain regions by the diffusion and removing the third insulating layer. LSI circuits with a high source-drain breakdown voltage may be fabricated at high yields.

REFERENCES:
patent: 3825442 (1974-07-01), Moore
patent: 3986896 (1976-10-01), Veno et al.
patent: 3986903 (1976-10-01), Watrous
patent: 4079504 (1978-03-01), Kosa
patent: 4102733 (1978-07-01), De La Moneda et al.
patent: 4114256 (1978-09-01), Thibault et al.
patent: 4151631 (1979-05-01), Klein

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