Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
1996-05-28
2001-01-16
Rose, Robert A. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C427S249300
Reexamination Certificate
active
06174222
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a fabrication technique of a semiconductor device, particularly to a semiconductor wafer (hereinafter called “wafer”) for use in a so-called pre-step among fabrication steps of the semiconductor device. More specifically, the present invention relates to a technique useful for the fabrication of a semiconductor integrated circuit device (hereinafter abbreviated as “IC”).
In general, IC is obtained by forming an integrated circuit including a semiconductor device (said integrated circuit including a semiconductor device will hereinafter be called “integrated circuit”) for each of a number of pellet divisions on the side of a primary surface of a wafer, separating the wafer into each pellet and then fabricating. In such a fabrication process of IC, it is necessary to finish the primary surface, on which an integrated circuit is to be made, as a mirror surface. In the case when only one of a pair of the primary surfaces is mirror-finished, it is easy to make discrimination between the obverse and reverse of the wafer. When the both sides of the wafer are mirror-finished, however, it becomes difficult to make discrimination between the observe and reverse of the wafer. Techniques have therefore been proposed in which an orientation flat (hereinafter abbreviated as “orifla”) for indication of the direction of a crystal axis is formed asymmetrically in a circumferential direction or in which a second orifla is formed for the discrimination between the obverse and reverse of a wafer.
An example describing a wafer whose observe and reverse can be discriminated without changing its circular shape is disclosed in Japanese Patent Utility Model No. 106821/1990. Described specifically, disclosed in it is a technique in which the obverse and reverse of the wafer are discriminated by the difference between the sizes of two chamfered corners defined by the obverse and the side surface of the wafer and the reverse and the side surface of the wafer.
As a wafer which can suppress the lowering of the rotation symmetry and in addition, increase the number of the semiconductor pellets (hereinafter called “pellets”), a wafer having a notch formed at the circumferential portion thereof (said wafer will hereinafter be called “notched wafer”) is known.
A notched wafer is disclosed, for example, in Japanese Utility Model Laid-Open No. 48020/1989. In it, a wafer in which the upper and lower edges of its ridgeline defining a notch have chamfered is disclosed. This notched wafer has a chamfered part formed at the notch so that the notch can be prevented from the damage upon application of a locating pin thereto in the IC fabrication step. As a result, the fabrication yield can be heightened.
In Japanese Patent Laid Open No. 240912/1990, disclosed is a notched wafer in which a notch formed at the circumferential portion thereof takes a form changing unsuccessively with the positional change toward the central direction and its plane shape is formed bilaterally asymmetrical in the circumferential direction. According to this notched wafer, the notch is formed bilaterally asymmetrical in the circumferential direction so that it is possible to discriminate the primary surface of the obverse from the primary surface of the reverse.
SUMMARY OF THE INVENTION
In a notched wafer, it becomes necessary to discriminate the obverse from the reverse, because an integrated circuit is fabricated on one side of a primary surface. And, it becomes extremely difficult to discriminate the observe from the reverse of the notched wafer if both sides have been mirror polished. For example, if the obverse and the reverse of the notched wafer are mistaken upon application of the wafer to a pre-fabrication step for IC, there is a danger of an integrated circuit being formed on a primary surface (reverse) of the notched wafer contaminated during handling or the like before application to the pre-fabrication step.
An object of the present invention is therefore to provide a notched wafer whose obverse and reverse can be discriminated and to provide a process for the fabrication of a semiconductor device capable of properly fabricating a semiconductor device by discriminating the obverse from the reverse of the notched wafer.
As disclosed in the above-described Japanese Patent Laid-Open No. 240912/1990, according to the notched wafer in which the plane shape of the notch is formed bilaterally asymmetrical in the circumferential direction, the primary surface on the obverse of the wafer can be discriminated from the primary surface on the reverse side of the wafer. The asymmetrical plane shape of the notch, however, causes damage to the rotation symmetry of the wafer, decreases the number of the pellets to be formed and besides, makes the notch in a special form outside the standards. It is therefore accompanied with the problem that a drastic reform becomes necessary in a positioning mechanism using a notch in a fabrication device used for the fabrication process of IC.
An object of the present invention is to provide a notched wafer permitting a discrimination between the obverse and reverse of the wafer while maintaining the symmetry of the plane shape of the notch.
Another object of the present invention is to provide a process for the fabrication of a semiconductor wafer by which said notched wafer can be fabricated rationally.
The above-described and other objects and novel characteristics of the present invention will be apparent from the description of this specification and drawings attached thereto.
Out of the aspects of the present invention disclosed in this application, representative ones can be summarized as follows:
The semiconductor wafer has a notch formed at the circumferential portion thereof and the notch comprises a chamfered portion formed at an inner periphery on one primary surface of the notch and a chamfered portion formed at an inner periphery on another primary surface, said chamfered portions being different each other.
According to the above-described means, the obverse and reverse of the semiconductor wafer can be discriminated by recognizing the difference between these chamfered portions. By distinguishing between the obverse and reverse of the semiconductor wafer, a principal surface on which a semiconductor device is to be fabricated can always be identified so that the semiconductor device can be fabricated properly by making use of such a structure of the semiconductor wafer.
There exists difference only in the chamfered portion and a plane shape of the notch can be maintained symmetrical in a circumferential direction. It is therefore possible to prevent a drastic deterioration in the symmetry of the semiconductor wafer and in the number of semiconductor device to be formed. In addition, by maintaining the standards for a notch, it is possible to avoid reforming of a notch-using positioning means of the existing fabrication system used for the fabrication of semiconductor devices.
Other aspects of the present invention disclosed in this application can be summarized briefly as follows:
1. A process for the fabrication of a semiconductor integrated circuit device comprising the following steps:
(a) a step of preparing plural silicon wafers of a substantially same shape for the fabrication of an integrated circuit, said silicon wafers each having an almost round and plane shape except the notched portion and having a mirror-polished first principal surface and second principal surface which are substantially parallel each other; and
(b) by judging the obverse and reverse of each of said plural wafers from the notched portion which has been formed at the peripheral portion corresponding to a predetermined crystal orientation of the wafer and has been chamfered to be plane asymmetrical to a reference plane, assuming that a plane parallel to and is equally distant from said first and said second principal surfaces is the reference plane, a step of performing by single wafer processing or batch processing at least one procedure out of wafer pr
Kanai Akira
Koike Atsuyoshi
Maejima Hisashi
Sato Tomomi
Shimizu Hirofumi
Hitachi , Ltd.
Nattingly, Stanger & Malur, P.C.
Rose Robert A.
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