Process for fabrication of merged transistor logic (MTL) cells

Details Process for fabrication of merged transistor logic (MTL) cells Process for fabrication of merged transistor logic (MTL) cells

1977-04-29

1979-04-17

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148187, 357 34, 357 91, 357 92, H01L 21265, H01L 2702, H01L 2122

Patent

active

041499069

ABSTRACT:
A method is disclosed to fabricate a Merged Transistor Logic (MTL) cell having vertical devices with higher beta and f.sub.T, and a lateral device with higher beta than available from conventionally fabricated cells. Features which contribute to these results include a p-type epitaxial layer, highly doped emitter and collector regions for the lateral PNP transistor, a contour for the base region of the lateral PNP which reinforces its transistor action in the bulk rather than at the surface of the epitaxial layer, a highly doped emitter for the vertical device, a uniform doping profile for the base region of the vertical device, dielectric isolation, and the use of heavily doped base regions to reduce injection of emitter current into inactive regions of the cell.

REFERENCES:
patent: 3873383 (1975-03-01), Kooi
patent: 3909307 (1975-08-01), Stein
patent: 4043849 (1977-08-01), Kraft et al.
patent: 4045251 (1977-08-01), Graul et al.
patent: 4075039 (1978-02-01), Sloan, Jr.
patent: 4076556 (1978-02-01), Agras-Guerna et al.
Tomisawa et al., "Vertical Injection Logic", IEEE, Solid St. Circuit, vol. SC-11, (1976) 637.
Mulder et al., "High Speed I.sup.2 L", IEEE, Solid St. Circuit, vol. SC-11, (1976) 379.
McGreivy et al., "Up-Diffused I.sup.2 L -- -- -- ", Int..sup.n Electron Device Meeting, IEEE, Wash. D.C., Dec. 1976, p. 308.
Chang et al., "-- -- -- Bipolar -- -- -- Oxide & Diffused Isolation -- -- --".
Ibid, p. 577, Dec. 1975.

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