Process for fabrication of an all-epitaxial-oxide transistor

Details Process for fabrication of an all-epitaxial-oxide transistor Process for fabrication of an all-epitaxial-oxide transistor

2001-01-24

2002-02-26

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Having superconductive component

C438S003000, C438S104000

Reexamination Certificate

active

06350622

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuit devices and more particularly to transistors formed exclusively from epitaxial oxide layers.
2. Description of the Related Art
Silicon based metal oxide semiconductor field effect transistors (MOSFETs) are reaching the limits of scaling (e.g., reduction in size) due to, among other things, doping and double depletion effects. In other words, as semiconductor devices are reduced in size, the depletion regions are placed in closer proximity to one another. This often results in merging or shorting of the adjacent depletion regions.
Silicon MOSFET technology is expected to scale to 0.1 micron channel length devices after the year 2000. Below 0.1 microns however, there are fundamental physical effects which can limit silicon MOSFET technology, including: short channel effects, dopant number fluctuations, and ballistic transport and tunneling through thin gate oxides. These effects may limit the minimum channel length in silicon MOSFET technology to an estimated 30 nm.
One solution to the scaling problem is a field effect transistor (FET) formed with a channel oxide capable of undergoing a metal-insulator transition known as a Mott transition (e.g., a Mott FET or MTFET).
A Mott FET is a solid state switching device made of oxide materials and is discussed in more detail in
Mott Transition Field Effect Transistor
, Applied Physics Letters, Vol. 73, Number 6, pages 780-782, Aug. 10, 1998, incorporated herein by reference. The Mott FET device includes a channel connecting source and drain electrodes, a gate oxide and a gate electrode.
For example, a Mott FET device is shown in FIG.
11
. The device includes a conductive substrate
110
(e.g., Nb-STO (100)-cut crystal) which forms the gate electrode, a gate oxide layer
111
(e.g., strontium titanate (STO)) epitaxially grown on the substrate
110
, a Mott conductor-insulator transition channel
112
(e.g., epitaxially grown cuprate material such as Y
1-x
Pr
x
Ba
2
Cu
3
O
7-&dgr;
(YPBCO, LCO)), source and drain electrodes
113
and an isolation trench
114
. With the structure shown in
FIG. 11
, when an electric field is applied to the gate
111
, the channel
112
changes from an insulator to a conductor (or vice versa) to make or break a connection between the source and drain
113
.
The Mott FET device is quite distinct from conventional silicon metal oxide field effect transistors in that the channel is a Mott insulator, a material with a characteristic, controllable, conductor-insulator transition, used in place of a semiconductor. A Mott FET device offers significant potential for scaling to the nanometer dimensions for integration with ferroelectric materials in non-volatile storage roles and for fabrication of multilayer device structures. Mott FET devices remain adequate on a nanoscopic scale which is well beyond the current projected limits of silicon MOSFET scaling.
However, the Mott FET discussed above has a number of limitations. Specifically, the structure shown in
FIG. 11
results in the channel layer
112
being exposed to subsequent processing steps, which may damage or undesirably change the channel layer
112
.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for forming an integrated circuit chip having a transistor including forming a conductive oxide layer, forming a Mott transition oxide layer over the conductive oxide layer and forming an insulative oxide layer over the Mott transition oxide layer. Source and drain contacts are connected to the conductive oxide layer and a gate conductor is connected to the insulative oxide layer. The Mott transition oxide layer includes a channel region adjacent the gate conductor. The gate conductor contact connects to the same wiring level as the source and drain contacts. A release layer is formed on a substrate and the conductive oxide layer is formed on the release layer. The method further includes forming a flexible substrate over the insulative oxide layer and removing the substrate and the release layer. The Mott transition layer is a perovskite oxide. The forming of the conductive oxide layer, the Mott transition oxide layer, and the insulative oxide layer are performed using epitaxial growth processes.
Another embodiment of the invention is a method of forming a transistor and includes forming a strontium ruthanate layer, forming a perovskite oxide layer over the strontium ruthanate layer and forming a strontium titanate layer over the perovskite oxide layer. Source and drain contacts are formed connected to the strontium ruthanate layer and a gate conductor is connected to the strontium titanate layer. The perovskite oxide layer includes a channel region adjacent the gate conductor. The gate conductor contact connects to a same wiring level as the source and drain contacts. A release layer is formed on a substrate and the strontium ruthanate layer is formed on the release layer. A flexible substrate is formed over the strontium titanate layer and the substrate and the release layer are removed. The forming of the strontium ruthanate layer, the forming of the perovskite oxide layer and the forming of the strontium titanate layer are performed using epitaxial growth processes.
The invention also comprises an integrated circuit chip having a transistor that includes a conductive oxide layer, a Mott transition oxide layer over the conductive oxide layer and an insulative oxide layer over the Mott transition oxide layer. The integrated circuit chip includes source and drain contacts connected to the conductive oxide layer and a gate conductor connected to the insulative oxide layer. The Mott transition oxide layer includes a channel region adjacent the gate conductor. A gate conductor contact connects to a same wiring level as the source and drain contacts. The integrated circuit chip includes a release layer below the conductive oxide layer and a substrate below the release layer. The integrated circuit chip includes a flexible substrate over the insulative oxide layer. The Mott transition layer includes a perovskite oxide. The conductive oxide layer, the Mott transition oxide layer and the insulative oxide layer include epitaxially grown layers.
Therefore, the invention avoids the conventional problems associated with semiconductor structures. More specifically, with the invention, the size of the structures can be dramatically reduced because there are no diffusion regions and the size limitations imposed by doping restrictions and undesirable overlapping diffusion regions are avoided.


REFERENCES:
patent: 3783505 (1974-01-01), Schoen, Jr.
patent: 4395583 (1983-07-01), Meulenberg, Jr.
patent: 5418389 (1995-05-01), Watanabe
patent: 6121642 (2000-09-01), Newns

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