Process for fabricating ULSI CMOS circuits using a single polysi

Details Process for fabricating ULSI CMOS circuits using a single polysi Process for fabricating ULSI CMOS circuits using a single polysi

1994-10-04

1995-04-11

Quach, T. N.

Fishing, trapping, and vermin destroying

437 44, 437 57, 437228, H01L 21336, H01L 218238

Patent

active

054057914

ABSTRACT:
This invention is a process for fabricating ultra-large-scale integration CMOS circuits using a single polysilicon gate layer for both N-channel and P-channel devices, a single mask step for defining the gates of both N-channel and P-channel devices, the fabrication of one set of disposable spacers for N-channel implants, and the fabrication of another set of disposable spacers for P-channel source/drain implants. The set of spacers used for P-channel implants also comprises material deposited to fabricate the spacers for the N-channel implants. The process is adaptable to LDD structures for both N-channel and P-channel devices or for only N-channel devices. The process is also compatible with anti-punchthrough implants for both types of devices.

REFERENCES:
patent: 4722909 (1988-02-01), Parillo et al.
patent: 4745086 (1988-05-01), Parillo et al.
patent: 4753898 (1988-06-01), Parillo et al.
patent: 4764477 (1988-08-01), Chang et al.
patent: 4771014 (1988-09-01), Liou et al.
patent: 4818714 (1989-04-01), Haskell
patent: 4968639 (1990-11-01), Bergonzoni
patent: 4994404 (1991-02-01), Sheng et al.
patent: 5010030 (1991-04-01), Pfiester et al.
patent: 5015595 (1991-05-01), Wollesen
patent: 5021354 (1991-06-01), Pfiester
patent: 5024959 (1991-06-01), Pfiester
patent: 5087582 (1992-02-01), Campbell et al.
patent: 5234850 (1993-08-01), Liao
Pfiester et al., "An Advanced 0.5-um CMOS Disposable TiN LDD/Salicide Spacer Process", IEEE Electron Device Letters, vol. 11, No. 7, Jul. 1990, pp. 318-320.
Pfiester, J., et al., "A Poly-Framed LDD . . . ", IEEE Elect. Device Letters, vol. 11, No. 11, Nov. 1990, pp. 529-531.
Parillo, L., et al., "Disposable Polysilicon LDD Spacer . . . ", iEEE Trans. Elect. Devices, vol. 38, No. 1, Jan. 1991, pp. 39-46.
Pfiester, J., et al., "An Integrated 0.5 .mu.m CMOS . . . " IEEE IEDM Tech. Digest, Dec. 1989, pp. 781-784.
Ronkainen, H., et al., "The Use of Disposable Double Spacer . . . ", IEEE Electron Device Letters, vol. 12, No. 3, Mar. 1991, pp. 125-127.
Lu, C., et al., "Submicrometer Salicide CMOS Devices . . . ", IEEE Electron Device Letters, vol. 19 No. 11, Nov. 1989, pp. 487-489.

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