Process for fabricating two loads having different resistance le

Details Process for fabricating two loads having different resistance le Process for fabricating two loads having different resistance le

1994-02-18

1996-09-10

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437191, 437918, H01L 218244

Patent

active

055545548

ABSTRACT:
The present invention provides a method of forming a first load having a first resistance level and a second load having a second resistance level in a common layer of polysilicon. In accordance with the method, a layer of polysilicon having a first resistance level is formed on a semiconductor circuit structure. A mask is then formed on the polysilicon layer to define areas of the polysilicon to be implanted with a dopant. The dopant is then implanted into the defined areas of the polysilicon to modify these areas to have a second resistance level. Selected areas of the polysilicon layer are then etched away to form first load regions having the first resistance level and second load regions having the second resistance level.

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English translation of Yamanochi-JP-62-166522.
English translation of Ogawa-0048027.

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