Process for fabricating static random access memory having stack

Details Process for fabricating static random access memory having stack Process for fabricating static random access memory having stack

1995-06-15

1996-11-19

Tsai, H. Jey

Fishing, trapping, and vermin destroying

437915, 437918, H01L 2170, H01L 2700

Patent

active

055762387

ABSTRACT:
A process for fabricating memory cells of a static random access memory (SRAM) device is disclosed to reduce the required die area and increase storage capacity. Each of the memory cells of the SRAM comprises a group of four MOS transistors, a pair of resistors, a pair of bit lines, as well as a word line. The process of fabrication the memory cells of the SRAM device comprises a number of process steps that are implemented subsequently on the surface of said semiconductor substrate, with the first and second MOS transistors first formed on the semiconductor substrate. According to the process, the first and second resistors are then formed on top of the first and second MOS transistors. Then the third and fourth MOS transistors and a word line are subsequently formed on top of the first and second resistors. Finally, the first and second bit lines for the memory cells are formed on top of the third and fourth MOS transistors. The process for fabricating the memory cells is characterized by the fact that the third and fourth MOS transistors are fabricated as vertical conduction transistors having their drains, sources and gates aligned substantially in a direction orthogonal to the plane of the semiconductor substrate.

REFERENCES:
patent: 4656731 (1987-04-01), Lam et al.
patent: 4828629 (1989-05-01), Ikeda et al.
patent: 5116775 (1992-05-01), Katto et al.

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