Process for fabricating stacked trench capacitors of dynamic ram

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437 38, 437 47, 437 51, 437 60, 437191, 437193, 437203, 437228, 437233, 437235, 437919, H01L 2170

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050266594

ABSTRACT:
A process for fabricating a stacked trench capacitor of a DRAM by way of the anisotropic dry etch technique of CVD silicon. In the process, sidewalls are formed by the anisotropic dry etch of CVD silicon which is formed within a trench for good electrical isolation between trenches, and upon the wet etch of an oxide film, are served as blocking layers to leave an oxide film layer for isolation in the side surfaces of the trenches. In the bottom part of the trenches in which the oxide film is removed, the ion implantation is performed with dopants having an opposite type in relation to the impurity diffusion area of a transistor for isolating the whole of the trenches effectively. Also, on the slant trench in which sharp edges do not exist the thin dielectric layer is formed to eliminate electrical weakspots.

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patent: 4939104 (1990-07-01), Pollack et al.
Toru Kaga et al., "Half Vcc Sheath-Plate Capacitor Dram Cell With Self-Aligned Buried Plate Wiring", IEEE Transaction on Elect. Devices, vol. 35, No. 8, Aug. 88, pp. 1257-1263.
Watanake, H., Kurosawa, K. and Sawada, S., Stacked Capacitor Cells for High-Density Dynamic RAMS, 88 IEDM, 600-603, 1988.
Horiguchi, F., Nitayama, A., Hieda, K., Hamamoto, T., Tsuda, K., Sunoushi, K., Takenouchi, N., Aritome, S., Takato, H. Kimura, M., Yamake, K., Nakase, M., Kamata, Y., and Masuoka, F., Process Technologies for High Density, High Speed 16 Megabit Dynamic RAM, 87 IEDM 324-327, 1987.

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